Abstract: A digital micromirror device (DMD) modified for use as a temporal light modulator. The DMD is modified so that the mirrors of the DMD have a preferential tilt direction. The inputs and outputs of the DMD are connected to common ground, except for the bias input lines. The latter are connected to a common excitation input, which is used to cyclically reposition the mirrors between tilted and flat states.

Abstract: Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

Abstract: A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment; and said gold layer providing a visual distinction to said areas.

Abstract: The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (802). A short delay polarization value is obtained (804) by writing a data value, performing a short delay, and reading the data value. A long delay polarization value is obtained (806) by again writing the data value, performing a long delay, and again reading the data value. The short delay and long delay polarization values are compared (808) to obtain a data retention lifetime for the ferroelectric memory device. The obtained data retention lifetime is compared with acceptable values (810) and, if deemed unacceptable, avoids unnecessary performance of thermal bake data retention lifetime testing.

Abstract: Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the substrate to form an aperture (210) over a desired portion of the substrate near its outer edge. A buffer material (214), selected to impede mobile charge ingress, is implanted (310) through the aperture into the insulator layer (304) of the substrate to form a buffer structure (312).

Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

Abstract: Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to unobtrusively measure the power consumption of an embedded application as the application is executing on its target hardware. The unobtrusiveness is achieved by using programmable emulation circuitry in the target system processor and available device debug terminals on the test port.

Abstract: A digital transceiver operative for direct sequence spread spectrum communications is described, a master counter associated with a zero offset pseudorandom noise (PN) sequence; a slave counter associated with a demodulating finger; and a counter output of said master counter coupled to a counter input of said slave counter.

Abstract: A frequency division multiplexing wireless transmission on two or more antennas with the set of symbols on subcarriers of a burst transmitted by one antenna transformed into another set of symbols on the subcarriers for the corresponding burst transmitted by another antenna. This helps overcome fading of the wireless channel by diversity.

Abstract: A device with a semiconductor chip (801) assembled on a planar substrate (802) and encapsulation compound (810) surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area (811). The encapsulation compound has a plurality of side areas (812) reaching from the substrate to the top area; these side areas form edge lines with the top area, where the top area plane intersects with the respective plane of each side area. The encapsulation compound is recessed (813) along the edge lines so that the material is caved-in along the lines; this feature causes the recess to prevent any compound from the side area planes to reach the top area plane, whereby the planarity of the top area is preserved.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).

Abstract: A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

Abstract: According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes determining that the data set associated with the wafer is useable and generating a probe map of the wafer from the data set. The probe map identifies a physical position associated with each unprobed die supported on the surface of the wafer. The probe map and one or more probe commands are communicated to a probe module to drive the probe module in resuming the probe of the wafer.

Abstract: An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device layer 20 is formed on the outer surface of buried insulator layer 18. An inductive well 22 can be formed to provide a platform for the formation of inductive devices 34 within an inductive region 26.

Abstract: A micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network system is disclosed. The micromirror array assembly (10, 20) includes a plurality of mirrors (29) monolithically formed with a frame (43), attached by way of hinges (55) and gimbal portions (45). Permanent magnets (53) are attached to each of the gimbal portions (45) associated with the mirrors (29). The resulting frame (43) is then mounted to a coil driver assembly (50) so that coil drivers (34) can control the rotation of each mirror (29), under separate control from control circuitry (14, 24). The micromirror array assembly (10, 20) is thus able to support higher signal energy at larger spot sizes, and also enables multiplexed transmission and receipt, as well as sampling of the received beam for quality sensing.

Abstract: A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word line driver coupled to word lines of the SRAM array and configured to operate at a word line driver voltage and (2) a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.

Abstract: The present invention provides a system (100) for conditioning multi-component slurries utilized in chemical mechanical polishing (CMP) of semiconductor wafers (140). The system provides a first slurry component (108), and a second slurry component (120). A conditioning component (102) has first and second inlets, and an outlet operatively coupled to a dispensing system (138). First and second flow control components (116, 126) are operably intercoupled between the first and second inlets and the first and second slurry components, respectively. The system further provides a megasonic energy source (106), adapted to generate an energy field (118) across the conditioning component. A conveyance component (114) conducts the slurry components from the inlets through the energy field, and delivers a final mixture (136) of multi-component slurry to the outlet.

Abstract: A method for processing semiconductor wafers includes processing a semiconductor wafer in a processing chamber having upper and lower chambers, decoupling the upper chamber from the lower chamber, cleaning the upper chamber, determining, while decoupled, that a leak rate and a particle count for the upper chamber meets predetermined criteria, and coupling the upper chamber to the lower chamber.

Abstract: An apparatus for electrical testing having probes (201) constructed of metal elements (201a) of about equal size bonded together in substantially linear sequence. Further an insulating holder (202) having first and second surfaces and a plurality of metal-filled vias (210) traversing the holder from the first to the second surface; the vias form contact pads on the first and second surfaces. The contact pads (210a) of the first holder surface have a probe attached so that the probe is positioned about normal to the surface. A sheet (203) of resilient insulating material, which has first and second surfaces and a thickness traversed by a plurality of conducting traces (220), has its first sheet surface attached to the second holder surface so that at least one of the traces contacts one of the contact pads, respectively, to provide an electrical path to the second sheet surface.

Abstract: A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.