Abstract: A method of communicating a data bit between memory devices is disclosed, having the steps of: indicating a first value of the data bit by transitioning, between state values, a first signal applied to a first communication line interconnecting the devices; and indicating a second value of the data bit by transitioning, between the state values, a second signal applied to a second communication line interconnecting the devices. Only one of the first and second signals may transition between the state values at any one time.

Abstract: The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

Abstract: A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47).

Abstract: A personal information manager (PIM) has been provided for use in controlling telephone call message responses for a wireless communications network mobile station telephone. The PIM permits a telephone user to program a unique response for each calling party. Typical responses including the normal audible alert, automatically transferring the call to voice mail, and silent ringing with no voice mail, to name but a few options. In addition, the matrix of calling parties and corresponding message responses can be modified for different times of the day or circumstances. For example, the PIM can be programmed to deliver a different set of responses during normal work hours than the responses provided at night, or during a business meeting.

Abstract: System and method for enabling signal acquisition in a satellite positioning system (SPS) when signals from SPS satellites are attenuated by the operating environment of a SPS receiver. A preferred embodiment comprises a communications server (for example, communications server 220) coupled to a SPS receiver (for example, SPS receiver 210) at one end and a time server (for example, time server 225) by a public network (for example, the Internet 230). Preferably, the communications server 220 is coupled to the Internet 230 via a wireless network to facilitate maximum mobility and flexibility. The communications server 220 queries the time server 225 for the current time and then provides the current time to the SPS receiver 210. The SPS receiver 210 makes use of the current time to assist it in signal acquisition.

Abstract: A method comprising downloading a boot image onto a mobile communication device and generating a device-bound certificate (“DBC”). The DBC preferably comprises an authentication code generated using a hashed message authentication code algorithm and a key specific to the device. The method may further comprise storing the DBC on the boot image, thus binding the boot image to the mobile communication device.

Abstract: System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.

Abstract: A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in order to gain a full understanding of how code is being executed by the processor.

Abstract: A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a different work function. The work function of each transistor type is determined by selecting a thickness of a corresponding semiconductor gate electrode and a thermal budget of a first thermal step such that, during silicidation, different silicide phases are obtained on the nMOS and the pMOS transistors. The work function of each type of transistor can be adjusted by selectively doping the semiconductor material prior to the formation of the silicide.

Abstract: In a method and system for controlling a direct current to direct current (DC-DC) converter includes an inductor coupled to receive a voltage input at an input terminal. A diode is coupled in series between the inductor and an output terminal of the DC-DC converter. A switch is coupled between the inductor and a ground reference. The switch receives a control signal from a controller for adjusting a duty cycle of the DC-DC converter. The duty cycle controls an output voltage at the output terminal. The controller generates the control signal in response to receiving a feedback signal, which is derived as a predefined function of a voltage feedback signal indicative of the output voltage and a current feedback signal indicative of a current flowing through the inductor.

Abstract: A field emission device 100 comprises an anode 105 and a cathode 110 separated by a distance 115 from the anode. At least one of the anode or cathode is configured to move with respect to the other in response to an applied voltage 120 to at least one of the anode and cathode, the distance being adjustable by the movement.

Abstract: The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.

Abstract: Overcurrent and overload protection for the power output of a pulse-width-modulated digital audio system is disclosed. The overcurrent protection circuitry includes a latch that is set in responsive to output current from the power output stage that exceeds an overcurrent threshold; the output of the latch gates the pulse-width-modulated control signal to block power output for the remainder of the current pulse-width-modulated cycle; upon the end of the cycle, or the beginning of the next, the latch is cleared to enable power output in that next cycle. Overload protection is provided by circuitry including counters for counting the relative number of overcurrent cycles to normal, non-overcurrent cycles, and generating an overload signal to block power output in the event of too frequent overcurrent cycles.

Abstract: In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and an integrated circuit including the same. In one embodiment of the present invention, the interconnect structure includes a conductive feature (150) located in or over a dielectric layer (140), and a silicon oxycarbonitride layer (160) located over the conductive feature (150).

Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Abstract: The present invention provides a process for increasing the hermeticity of a hermetic layer, a method for manufacturing an interconnect structure, and a method for manufacturing an integrated circuit. The process for increasing the hermeticity of the hermetic layer, without limitation, includes providing a hermetic layer over a substrate (160), the hermetic layer having a initial hermeticity, and subjecting the hermetic layer to an energy beam, thereby causing the initial hermeticity to improve (170).

Abstract: The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple data sources, including building one or more single-source data words by iteratively selecting a data source, writing data from the data source to each data section within a single-source data word if enough data is available to fill the single-source data word, copying a data bit of the single-source data word to a data bit within a start word, and clearing the data bit of the single-source data word; and including transmitting the one or more single-source data words after transmitting both a start word and one or more multi-source data words within the same data frame The data written into the one or more single-source data words and the data most recently written into the one or more multi-source data words originate from the same data source.

Abstract: A solid-state image sensor has a readout architecture that incorporates charge multiplier cells into a horizontal register of a CCD image sensor, and includes a first CCD register adjacent to at least a second CCD register and coupled to the said first register through a charge overflow barrier. A high Dynamic Range readout system results in which the DR is not restricted by the voltage swing limitations on the charge detection node. As the charge is multiplied, the horizontal register structure increases in width and more charge multiplication gates are added per stage. A charge overflow region follows the charge multiplier. In this region the amount of charge that exceeds a certain predetermined threshold is split off into another register. A detection node that has different conversion sensitivity may terminate this register. The process of charge overflow and splitting off may continue for more than two steps.

Abstract: Method and apparatus for OFDM synchronization and channel estimation. In a temporal embodiment, received embedded system pilot symbols are inverse Fourier transformed at expected index locations and correlated with computed complex conjugates of inverse Fourier transforms of pilot symbols for providing a correlation function for the channel impulse response. In a frequency domain embodiment, embedded system pilot symbols are augmented with pilot-spaced inferred guard band symbols, multiplied by scaled complex conjugates of computed pilot systems, and inverse Fourier transformed into the channel impulse response. Time and frequency are synchronized in feedback loops from information in the channel impulse response. The channel impulse response is filtered, interpolated, and then Fourier transformed for determining channel estimates for equalization.