Patents Assigned to Texas Instruments
  • Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same
    Publication number: 20060259883
    Abstract: The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator also includes a distributed parameter allocator coupled to the parasitic element extractor and configured to provide a distributed model of the passive integrated circuit device and allocate the parasitic elements within the distributed model based on the surrounding layout environment.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Inc.
    Inventors: Isaac Cohen, Sergey Komarov
  • METHOD AND SYSTEM OF IDENTIFYING OVERLAYS
    Publication number: 20060259826
    Abstract: A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of overlays of the traced program has executed on the target system, and displaying on a display device an indication of a proportion of an execution time on the processor of the target system dedicated to each of the plurality of overlay programs.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gary Swoboda, Oliver Sohm, Brian Cruickshank, Manisha Agarwala
  • EVENT AND STALL SELECTION
    Publication number: 20060259162
    Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • EVENT AND STALL SELECTION
    Publication number: 20060259164
    Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • SELECTIVELY EMBEDDING EVENT-GENERATING INSTRUCTIONS
    Publication number: 20060259750
    Abstract: An information carrier medium containing debugging software that, when executed by a processor, causes the processor to receive information from hardware in communication with the processor, the information indicative of one or more no-operation instructions (NO-OPs) in software code stored on the hardware. The software also causes the processor to selectively replace at least one of the NO-OPs with an event-generating instruction (EGI). When executed, the EGI causes a circuit logic to generate one or more events.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects
    Publication number: 20060258142
    Abstract: The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Asad Haider, Alfred Griffin, Kelly Taylor
  • DETERMINING OPERATING CONTEXT OF AN EXECUTED INSTRUCTION
    Publication number: 20060259823
    Abstract: Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace program that, when executed by a processor, causes the processor to display trace data on a display device (the trace data comprising a plurality of addresses of instructions executed by a target processor), enable a user of the debug-trace program to select an address of the plurality of addresses to create a selected address, and display data based on an operating context proximate in time to when the instruction of the selected address was executed on the target processor.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank
  • PROFILING SYSTEM
    Publication number: 20060259822
    Abstract: A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit (the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program), a first memory operatively coupled to the processing circuit (the first memory comprising instructions to be executed by the processing circuit), and a memory location operatively coupled to the trace system (the memory location writable by the target program). The trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments incorporated
    Inventor: Gary Swoboda
  • CROSS-REFERENCING CACHE LINE ADDRESSES WITH CORRESPONDING NAMES
    Publication number: 20060259697
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels. The caches comprise a plurality of cache line addresses, each cache line address associated with a corresponding name. The software causes the processor to display the information on a graphical user interface (GUI), the GUI cross-referencing each of the cache line addresses with a corresponding name.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver SOHM, Brian Cruickshank
  • REAL-TIME PRIORITIZATION OF STALL OR EVENT INFORMATION
    Publication number: 20060259664
    Abstract: Disclosed herein is a system and method for executing a series of instructions on a circuit. An encoder receives event data corresponding to the executed instructions, wherein the encoder groups the event data into one or more groups and outputs the highest priority event for each group.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Oliver Sohm
  • Akrion solvent hood robot arm, non-warp modular design
    Publication number: 20060254379
    Abstract: In a method and apparatus for handling semiconductor materials, a robot arm includes a tubular shaft having a distal end and a proximal end. A distal block disposed over the distal end is detachably secured to the distal end and a proximal block disposed over the proximal end is detachably secured to the proximal end. The tubular shaft, which has an adjustable length, is formed from a warp-resistant material that has sufficient strength to maintain a longitudinal axis alignment of the tubular shaft within a predefined tolerance. The distal block and the proximal block are customized to substantially match corresponding features of a legacy robot arm, thereby enabling a complete replacement of the legacy robot arm.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gregory Burchyett
  • DETERMINING THE PRESENCE OF A VIRTUAL ADDRESS IN A CACHE
    Publication number: 20060259693
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank
  • DETERMINING DIFFERENCES BETWEEN CACHED COPIES OF AN ADDRESS
    Publication number: 20060259696
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to determine a difference between the information from caches on different cache levels associated with the common address and to provide the difference to a user of the software.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda, Jagadeesh Sankaran, Bradley Caldwell
  • Method for forming fully silicided gates and devices obtained thereof
    Publication number: 20060258156
    Abstract: A method for manufacturing fully silicided (FUSI) gates and devices, in particular MOSFET devices, is described. The method includes deposition a metal layer over a semiconductor layer of a gate stack, providing a first thermal budget to allow a partial silicidation of the semiconductor layer, selectively removing a remaining unreacted metal layer, and providing a second thermal budget to allow a full silicidation of the semiconductor layer. As a result, the silicide phase can be effectively controlled.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Texas Instruments Inc.
    Inventor: Jorge Kittl
  • MONITORING OF MEMORY AND EXTERNAL EVENTS
    Publication number: 20060259751
    Abstract: A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also comprises a monitoring device coupled to the circuit. The monitoring device receives information about said event data. The event data comprises event data selected from a group consisting of memory events and external events.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Gary Swoboda, Manisha Agarwala
  • METHOD AND SYSTEM OF PROFILING APPLICATIONS THAT USE VIRTUAL MEMORY
    Publication number: 20060259825
    Abstract: A method and system of profiling applications that use virtual memory. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of tasks, each task using a different virtual to physical memory mapping), obtaining values indicative of a plurality of states of virtual to physical memory mapping used by a memory management unit associated with a processor of a target system, and displaying an indication of a proportion of an execution time the processor of the target system dedicated to each of a plurality of tasks during the execution time.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Brian Cruickshank, Oliver Sohm
  • Novel method for manufacturing a semiconductor device containing metal silicide regions
    Publication number: 20060258091
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Inc.
    Inventors: Juanita DeLoach, Lindsey Hall, Lance Robertson, Jiong-Ping Lu, Donald Miles
  • WATERMARK COUNTER WITH RELOAD REGISTER
    Publication number: 20060259774
    Abstract: A series of instructions from executable code are implemented on a processor core which in turn outputs event data. A watermark counter inputs event data and counts the number of events that occur within a time period defined by a start and stop signal. The watermark counter outputs a count value, corresponding to the number of events counted in the time period, across a connection to a monitoring computer.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gary Swoboda, Jason Peck
  • BYPASSING CACHE INFORMATION
    Publication number: 20060259694
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to selectively bypass a portion of the information specified by a user of the software and to provide non-bypassed information to the user and not said bypassed portion.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda, Jagadeesh Sankaran
  • SYSTEMS AND METHODS FOR CONTROLLING ACCESS TO SECURE DEBUGGING AND PROFILING FEATURES OF A COMPUTER SYSTEM
    Publication number: 20060259828
    Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda