Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.

Abstract: A speech encoder/decoder for wideband speech with a partitioning of wideband into lowband and highband, convenient coding of the lowband, and LP excited by noise plus some periodicity for the highband. The embedded lowband may be extracted for a lower bit rate decoder.

Abstract: The present invention achieves technical advantages as an operational amplifier (30) having both a high slew rate and a full power bandwidth with low distortion by providing resistors (R6, R7, R9, R10) in place of active loads coupled to a differential pair (Q22, Q25, and Q23, Q24) of transistors in a folded cascode input stage (34). By utilizing passive resistors instead of active loads, no saturation occurs during high slew rate signals. The present invention achieves technical advantages of higher slew rate and lower noise without sacrificing power consumption.

Abstract: A transmitter architecture (200) provides for a stable and low noise modulator where the modulation bandwidth is uncorrelated to the TX loop bandwidth. The output signal (228) of the TX loop is demodulated by a demodulator (208) and the demodulated signal is compared by a comparator (206) with the modulating input signal (202). The output of the comparator is then used to adjust a digital pre-emphasis filter (204) which preconditions the modulating input signal (202) in the digital domain. The preconditioning approach of the present invention provides for low noise because the transmitter designer can chose a narrow band for the TX loop which will also filter out the noise coming from the additional synthesizer (226) used to down convert the input signal.

Abstract: Circuits and methods for dynamically stabilizing a circuit having a relatively small capacitive load two current loop sub circuits are provided. A main current loop and an associated sensing loop are coupled such that a compensation capacitance supplied to each sub circuit loop individually will remain isolated and will not be cumulative with respect to the remainder of the circuit.

Abstract: A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Abstract: Detecting a boundary between training sequences in a transmission is an important operation. In many communications systems, there are no special boundaries or markers to denote the end of one sequence and the beginning of another. Correlation has been a commonly used technique to detect sequences and a fall in the correlation can be used to indicate such boundaries, but classical correlation can be slow and a significant portion of the new sequence is received prior to the boundary being detected. A method and apparatus is presented that allows rapid detection of the boundary and only a small amount of the new sequence needs to be received prior to the detection of the boundary. Additionally, the method and apparatus can be used to detect the presence of a transmission on the communications medium.

Abstract: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate (301) with first and second surfaces (301a, 301b), at least one opening (310), and a certain thickness (302). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads (330); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body (901) attached. A semiconductor chip (102) is positioned in the opening while leaving a gap (311) to the substrate; the chip has an active surface (102a) including at least one bond pad (103), and a passive surface (102b) substantially coplanar with the second substrate surface (301b). Substrate thickness and chip thickness may be substantially equal. Bonding elements (501) bridge the gap to connect electrically bond pad and routing strip.

Abstract: A digital audio processor (20) is disclosed, in which digital filter coefficients associated with a plurality of sampling frequencies are stored in a plurality of coefficient memory banks (55). A controller in the digital audio processor (20) selects one of the coefficient memory banks (55) for use in the digital signal processing channels (44). In a manual mode, this selection is in response to a manual selection entry in a bank control register (41). In an automatic mode, indicated by a specific entry in the bank control register (41), sample rate detector circuitry (54) detects the sampling frequency relative to an external reference, such as a crystal (XTL); the appropriate one of the coefficient memory banks (55) is then selected based on sampling frequency associations stored in rate select register (43) in the controller (40).

Abstract: The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme (300) includes a protective layer (320) located over a substrate (310), and a conductive layer (330) located over the protective layer (320). The metallization scheme (300) further includes a stress-reducing low-modulus material (340) located between the protective layer (320) and the conductive layer (330).

Abstract: In an optical wireless network, where light beams are transmitted over-the-air, reflections of the transmitted light beams may cause a receiver of an optical wireless device to detect and subsequently lock onto the signal that it transmitted. By doing so, the network is effectively broken. A method and apparatus to detect the reception of reflected signals using minimal additional hardware and data is presented. Should a reflected signal be detected, the receiver is prevented from locking onto the signal, allowing the receiver to detect and subsequently lock onto light beams originating from other optical wireless devices.

Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.

Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.

Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.

Abstract: Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800).

Abstract: A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.

Abstract: A method for implementing a plurality of backoff counters on a hardware backoff counter for use in implementing a prioritized message transmission network is presented. A message with a smallest backoff time is selected and placed into the hardware backoff counter. When the hardware backoff counter expires, the message is transmitted. Whenever the communications medium becomes busy, the backoff time for every message is updated.

Abstract: A linear transformation of parallel space-time transmit diversity encoded streams; also, asymmetrical symbol mapping of parallel streams. Separately or together, these improve error rate performance as well as system throughput. Preferred embodiments include CDMA wireless systems with multiple antennas.

Abstract: A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.