Abstract: Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of operating at one or more security levels including a first and a second security level, a memory system coupled to the processor (the memory system stores a first program that executes on the processor at the first security level, and a second program that executes on the processor at the second security level), and a register configured to store an entry point address to the first program (wherein an instruction that executes on the processor at the second security level is blocked from writing values to the register). A transfer of control from the second program to the first program is executed if the register provides the entry point address. The transfer of control is blocked if the entry point address is not provided by the register.

Abstract: Profiling operating context. At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to obtain values indicative of a state of an operating context parameter during execution of a traced program on a target processor, and display an indication of a proportion of time during a trace period of the traced program that the target processor operated with the operating context parameter in a particular state.

Abstract: Navigating trace data. A traced program, or the operating system responsible for the traced program, writes index values to a particular hardware location, which index values become part of the trace data by operation of hardware devices in the target system. A debug-trace program (executed either in an attached host computer or as an embedded debugger) uses the index values to assist the user of the debug-trace program in navigating to particular portions of the trace data based on the index values.

Abstract: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. Each of the caches comprises a plurality of cache lines, and each cache line is associated with a way. The software also causes the processor to reassign the way of a cache line to a different way.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to provide the information to a user of the software. At least some of the caches on different cache levels are associated with multiple processor cores.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises valid bit and dirty bit information associated with the caches on different cache levels.

Abstract: A method for collecting communication system information from a communication system including a controller and one or more communication devices operating therein includes transmitting a request to the one or more communication devices requesting information regarding a quality of signal(s) received at the one or more communication devices along with geographical location information from the one or more communication devices, and transmitting automatically from the one or more communication devices the signal quality information along with the geographical location information to the controller. A communication device which can automatically provide signal quality and location information is also described, as well as a communication system that can collect signal quality and geographical location information from one or more communication devices operating within the communication system.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches having a common cache level. The software also causes the processor to prioritize the caches having the common cache level such that the caches are displayable as having different cache levels.

Abstract: A DC/DC converter circuit including an inductance 10, two controllable switches 12, 14 and a controller 16 for controlling the switches 12, 14 is configured so that it is able to operate in two permanently alternating operating time phases. The switches 12, 14 in the DC/DC converter circuit are arranged so that when the controller 16 is in the first operating time phase it closes the first switch 12 and opens the second switch 14 in achieving a flow of energy from the input of the DC/DC converter circuit to the inductance 10 and then when the controller 16 is in the second operating time phase it opens the first switch 12 and closes the second switch 14 in achieving a flow of energy from the inductance 10 to the output of the DC/DC converter circuit. Prior to switching from one operating time phase into the other operating time phase an intermediate time phase is inserted for safety reasons, in which both switches 12, 14 of the DC/DC converter circuit are briefly opened.

Abstract: A FIFO circuit includes a memory such as a register array having a plurality of storage locations. One or more data inputs can be coupled to the memory for receiving data that is to be stored therein. A control circuit controls the storage of data received from the one or more data inputs into the memory. In one embodiment, a particular one (e.g., memory location 0) of the plurality of storage locations is used as the location from which all data from the memory is outputted from. A multiplexer is used to move the data from within the memory into this particular memory location. The control circuit includes circuitry which allows for data received from the one or more data inputs to be stored substantially at the same time into the memory. In another embodiment, the FIFO circuit includes one data input for receiving data from a write bus and a second data input for receiving data from a read bus.

Abstract: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

Abstract: The present invention enables the use of a single passive adaptor (1500, 1800) for multiple types of flash media cards. The present invention provides this by implementing form factors with a detection scheme (1410, 1610) that notifies a host controller of the type of media card that has been inserted. The form factors and detection scheme can be designed to meet PCMCIA CardBus Plus standards.

Abstract: An embedded symmetrical multiprocessor system includes arbitration logic that determines which central processing unit has access to shared memory. Upon grant of access, the memory address is stored in a memory address register. An address compare circuit compares the access address of any other central processing unit with this stored address. Upon a match, the arbitration logic stalls the second accessing central processing unit until expiration of a programmable number of wait states following the first access. These wait states give the first central processing unit enough time to determine the state of a lock variable and take control of an operation protected by the lock variable. The application boot code can determine how long the read-check-write operation requires and program that value into the wait-state generator.

Abstract: The circuit provides a type of switching power supply device that can reduce the ripple voltage generated in the output when switching is performed in the step-down/step-up control mode. Control part (CTRL) operates as follows: corresponding to the detection value of input potential detecting part 20, the step-down control mode/step-up control mode is switched; in each control mode, the clock signal generated by comparator 50 corresponding to output potential Vout is fed back to primary circuit (PRI)/secondary circuit (SEC); in this case, corresponding to the control mode, multiplexer 60 switches the input sign of transconductance amplifier 40 corresponding to the control mode.

Abstract: Various circuits, systems and methods are disclosed for providing double-sampling sigma-delta modulator circuits. For example, circuits are disclosed that include an amplifier with an integrating capacitor, a switched capacitor conversion element that includes a single capacitor bank, and a control element that provides phase signaling that identifies at least two phases. In operation, charge present on the single capacitor bank is transferred to the integrating capacitor and the single capacitor bank is charged during one phase. During the other phase, charge present on the single capacitor bank is transferred to the integrating capacitor, and the single capacitor bank is discharged.

Abstract: According to one embodiment of the invention, a method of packaging ball grid arrays includes providing a substrate having a plurality of holes formed therein. Each hole is associated with a respective one of a plurality of contact pads formed on a first surface of the substrate. The method further includes disposing a plurality of balls within respective ones of the plurality of holes such that at least a portion of each ball projects outwardly from the first surface, and applying a force to each of the balls from above the first surface to couple the balls to the substrate.

Abstract: In a cable television (CATV) data communication network, channel throughput and communications robustness are increased in a manner that improves speed of data transmission while maintaining compatibility with existing specifications and equipment. Enhanced throughput can be realized using the return channel of the CATV network. Alternatively, data retransmission and/or diversity techniques can be used to improve throughput.

Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m?/? and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

Abstract: According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface adapted to couple a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion. The generally circular center portion encloses an area and has an attachment surface area that is less than the area enclosed by the generally circular center portion. The attachment surface area is adapted to couple an inner portion of the polishing pad to the platen. According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface coupling a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion.