Abstract: An analog-to-digital (A/D) converter system is provided that compensates for operating variations associated with one or more passive components of the A/D converter. In one aspect of the present invention, the A/D converter system comprises a sigma delta modulator having at least one passive component and a feedback path that includes at least one switched digital-to-analog converter (DAC), and a tracking reference generator that provides compensated reference signals to the at least one switched DAC for providing feedback to the sigma delta modulator. The compensated reference signals include inverse variations that cancel operating variations associated with the at least one passive component.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process scan input and produce a first scan output. The system 100 includes a second module 150 substantially similar to the first module 140. The second module 150 receives and processes scan input and produces a second scan output. The system 100 also includes a first component 180 to receive the first and second scan outputs and to produce a first output. The first output is used to determine whether the first and second modules 140 and 150 are functioning properly.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mixture comprises a second solvent, wherein the second solvent comprises a volatile organic liquid.

Abstract: An amplifier sharing technique in an analog to digital converter (ADC) in which a cascaded combination of a pre-amplifier and main amplifier is used to provide the required amplification for a first stage, and only the main amplifier is used to provide the amplification for the second stage. Switches and capacitors are used in conjunction such that the sampling and feedback capacitors of the first stage are connected across the cascaded combination in a first phase, and sampling and feedback capacitors of the second stage are connected across the main amplifier in a second phase. By appropriate choice of parameter values for various components, the second poles due to the pre-amplifier may be located at the higher frequency ranges obtaining the required unity gain bandwidth (UGB) without Miller compensation and/or additional gain.

Abstract: In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. An adhesion prohibitor 315, 325 may be applied so that a support 314, 324 does not adhere to both lid and substrate; the support 314, 324 may be prevented from adhering to both lid and substrate by a separate curing step. The arrangements and fabrication methods may be applied to many package types, including ball grid array (BGA) and land grid array (LGA) packages.

Abstract: The present invention provides the ability to use existing cable TV wires for home networking.

Abstract: An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while the other end (1203) of each member is operable for reflow attachment to external parts.

Abstract: A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

Abstract: According to various embodiments, there is a method of inspecting semiconductor wafers comprising comparing a value for each wafer in a lot of wafers to a mathematical model, where the values include data about at least one feature on the wafers, and where the mathematical model comprises a threshold value corresponding to the at least one feature, and further where values greater than the threshold value comprise an indication of a spin defect. The method can also comprise determining whether any of the values of the wafers in the lot are not greater than the threshold value, grouping into a group (P) those wafers whose values are not greater than the threshold value, and flagging for further inspection those wafers having values greater than the threshold value.

Abstract: A circuit to improve the SN characteristic of a tracking error signal. This tracking error detection circuit is formed as a push-pull system utilizing a quadrant type photo-detector and provided with 4 gain control amplifiers 20, 22, 24, and 26, 4 bottom envelope circuits 28, 30, 32, and 34, a pair of subtracting circuits 36 and 38, adding (subtracting) circuit 40, offset circuit 42, and gain control circuit 44. Bottom envelope circuits 28, 30, 32, and 34 are configured with a capacitor-type peak-hold circuit, for example, whereby bottom envelopes of RF signals SA, SB, SC, and SD given from light receiving areas A, B, C, and D of a photo-detector via gain control amplifiers 20, 22, 24, and 26 are detected, and bottom envelope signals SAbtm, SBbtm, SCbtm, and SDbtm representing the waveforms of the respective bottom envelopes are output.

Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.

Abstract: Apparatus and methods for removing jitter and stabilizing the feed back system of a torsional hinged device with minimal changes to the system. The stabilization is accomplished by introducing a selected amount of lateral motion (in addition to the rotational motion) by creating asymmetry in the oscillating device or the drive torque applied to the device.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: A technique is described to change the codec or MAC (message authentication code) size in a packet security unit for PacketCable communications during realtime voice transmissions is described. An algorithm that provides fast RC4 key advancing to prevent MIPS (millions of instruction cycles per second) overflow is used to perform codec or MAC size changes. The invention is performed without changing the keying material, where the sender and receiver must continue the RC4 encryption process from its state prior to the codec or MAC size change. A sender needs to preserve continuity of the timestamp across a codec change, since the timestamp reflects realtime. Changing the codec or MAC size is likely to change the frame parameters. To preserve continuity of the RC4 state and the timestamp across the codec/MAC size change, the sender TX and receiver RX generates a new frame number. The new frame number is applied to the first frame generated by the new codec or MAC size.

Abstract: A method of discriminating voice, data, and facsimile calls communicated through a voice-over-packet network. The gateway is provided with software which can identify the existence of an answer signal (ANS) or a modified answer signal (ANSam) communicated between an answering modem and an originating modem over a packet network during a voice state call. The originating gateway can generate an ANS tone according to the protocols of the originating modem, using an originating-side gateway, when the existence of the ANS signal is identified by the receiving-side gateway. The originating gateway also generates an ANSam tone according to the protocols of the originating modem, using the originating-side gateway, when the existence of the ANSam signal is identified by the receiving-side gateway.

Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.

Abstract: The present invention provides a transmitter. In one embodiment, the transmitter includes a coefficient circuit configured to generate coefficients of a set of basis waveforms that represent channel quality metrics and a transmit circuit that transmits the coefficients. The present invention also provides a receiver. In one embodiment, the receiver includes a receive circuit configured to receive coefficients of a set of basis waveforms that represent channel quality metrics and a reconstruction circuit configured to reconstruct the channel quality metrics from the coefficients.