Abstract: Short circuit protection is provided for an isolation component that has a parasitic diode as an inherent part of its construction. The isolation component may or may not be contained in an integrated circuit. In response to detecting a short circuit condition based on voltages at one or more input terminals of the integrated circuit, or based on current between the terminals, the isolation component is activated to facilitate current flow through the isolation component, such as to reduce total power dissipation in the isolation component during at least part of the short circuit condition.

Abstract: A number of basic equalization and demodulation structures have been shown to be appropriate for DMT systems depending on the channel, noise, and system parameters. These include single path, dual path, oversampled, and double rate structures. Using the fundamental computation units of two TEQs (FIR filters) and two FFTs, in conjunction with simple delays, downsampling and routing, single path, dual path, oversampled and double rate equalization structures can be realized from a common equalization structure.

Abstract: An improved level shifter circuit with AC feed-forward is disclosed. The integrated circuit device includes a first circuit part biased from a lower voltage supply and a second circuit part biased from a higher voltage supply. One of the circuit parts has an RS flip-flop with two complementary signal outputs and the other one has a signal input and a first and a second switching transistor. The first and the second switching transistors each have a current channel DC coupled in series with a respective cascode-connected transistor which is connected to a respective one of the signal outputs. One of these outputs is coupled to the input through a first feed-forward AC series circuit of an inverter and a first coupling capacitor, and the other output is coupled to the input through a second feed-forward AC circuit including a second coupling capacitor.

Abstract: In one embodiment, a method for wavelet analysis of one or more signals to determine one or more characteristics of one or more anomalies in a wire includes receiving a first signal from a detector that has scanned a magnetic field from a wire including an anomaly. The first signal corresponds to a second signal used to generate the magnetic field. The method includes calculating a wavelet analysis result from a wavelet analysis of the first signal. The wavelet analysis result corresponds to the second signal. The method includes accessing a library of one or more reference wavelet analysis results that each correspond to one or more known anomalies having one or more known characteristics and comparing the wavelet analysis result with one or more reference wavelet analysis results.

Abstract: A CMOS analog switch is provided that can handle negative input polarity. The semiconductor substrate wherein the analog switch is formed has a substrate area of n-conductivity type. First and second p-channel transistors are formed in the n-conductivity substrate area and each have a gate, a source connected to the input terminal and a drain connected to the output terminal. The analog switch further has a comparator for comparing a voltage level at the input terminal with ground level, a switch driven by an output of the comparator to selectively connect the n-conductivity area with the signal input terminal for a positive input voltage level or to ground for a negative input voltage level, and control circuitry providing gate control signals for the first and second p-channel transistors. The inherent substrate diodes are effectively kept from becoming conductive.

Abstract: According to one embodiment of the invention, a method for auto-boating includes supporting a tape substrate having first and second end portions on a boat, sandwiching the first and second end portions between respective ones of a pair of end sleeves and the boat, coupling a boat clip to the boat, and removing the end sleeves from between the first and second end portions and the boat clip.

Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

Abstract: A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions to be performed by a first number of logic gates. The computer specifies the design by steps. In one step, the program specifies a second number of logic gates to be included in the circuit for indicating a potential speed capability. The second number of logic gates is less than the first number of logic gates and provides voltage and delay characteristics comparable to the data path. The computer also specifies additional circuitry to be included in the circuit for indicating a potential speed capability, wherein the additional circuitry is for representing parasitic characteristics in the data path.

Abstract: A system for controlling a plurality of load devices includes a high-side system operative to source current relative to at least two associated outputs. A low-side system is operative to sink current relative to a plurality of associated inputs. A control system controls the high-side system and the low-side system according to a multiplexing scheme that is operative to provide current to selected load devices of the plurality of load devices connected between the associated outputs and the associated inputs. The system can be implemented as an integrated circuit for driving the plurality of loads, which can include LED's.

Abstract: Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is avoided in several contexts (e.g., when driving a transmission line, which causes reflections). In an embodiment, the gradual change is implemented using a combination of a current source and a capacitor. The capacitor is provided at an input of the gate terminal of a drive transistor, and a current source is used to control the rate at which the capacitor discharges. As a result, the drive strength of a buffer is controlled.

Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a plurality of selectable devices under test (DUT) overlying a substrate of the wafer; biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed; determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter; biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

Abstract: A multi-line ADSL modem (12) and network (10) whereby the multi-line ADSL modem (12) has connections to several ADSL modems (14) at a central office (CO) (16) through a master loop (18), shared loops (20, 22), and/or broadcast loops (84). The master loop (18) provides the basic connection between the multi-line ADSL modem (12) and the CO modem (14) at the central office (16) while maintaining regular telephone service. The shared loops allow the multi-line ADSL modem to share the transmission capacity with other modems. The multi-line ADSL modem is able to receive broadcast data from the central office where several loops are configured as a broadcast loop for downstream transmission only, but which can also be configured for upstream communication transmission only or in combination with downstream transmission to provide bi-directional broadband communications.

Abstract: A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220).

Abstract: A decoding approaching suitable for architectures such as Very Long Instruction Word (VLIW), in which throughput performance would be reduced in case if large blocks of conditional core are executed repetitively. Some of the code-words are received according to escape modes, which require different kinds of processing depending on specific mode. The decoding logic is partitioned into two parts, with the first part accessing entries in tables corresponding to code-words. The first part writes the symbol value retrieved from the accessed entry into an output buffer. In case of escape modes, the first part writes an intermediate decoded value to the output buffer, and an escape mode identifier retrieved from an accessed entry, and a position identifier in the output buffer for the symbol sought to be decoded in an intermediate buffer. The second part then performs the specific processing required for each entry in the intermediate buffer.

Abstract: According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element approximately between a plurality of desired positions by a generally periodic drive waveform. During a particular period of the drive waveform, the actual position of the optical dithering element is determined at a plurality of sample times. For each of the determined actual positions of the optical dithering element, a position error indicator is determined based upon whether the magnitude of the actual position is greater than, less than, or the same as a desired setpoint for the position of the optical dithering element. The method also includes generating an error signature for the particular period based on the determined error indicators and modifying the drive waveform in response to the error signature.

Abstract: A method for testing a circuit includes determining at least one performance characteristic of the circuit based on a functional relationship between excitation signals or on a functional relationship between measurement devices. The method is implemented either as a part of a built-in self test circuit of an integrated circuit or for production testing.