Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver Sohm, Brian Cruickshank, Jagadeesh Sankaran, Gary Swoboda
Abstract: Navigating trace data. A traced program, or the operating system responsible for the traced program, writes index values to a particular hardware location, which index values become part of the trace data by operation of hardware devices in the target system. A debug-trace program (executed either in an attached host computer or as an embedded debugger) uses the index values to assist the user of the debug-trace program in navigating to particular portions of the trace data based on the index values.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver SOHM, Brian CRUICKSHANK, Manisha AGARWALA, Gary Swoboda
Abstract: A method for collecting communication system information from a communication system including a controller and one or more communication devices operating therein includes transmitting a request to the one or more communication devices requesting information regarding a quality of signal(s) received at the one or more communication devices along with geographical location information from the one or more communication devices, and transmitting automatically from the one or more communication devices the signal quality information along with the geographical location information to the controller. A communication device which can automatically provide signal quality and location information is also described, as well as a communication system that can collect signal quality and geographical location information from one or more communication devices operating within the communication system.
Abstract: The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator also includes a distributed parameter allocator coupled to the parasitic element extractor and configured to provide a distributed model of the passive integrated circuit device and allocate the parasitic elements within the distributed model based on the surrounding layout environment.
Abstract: A series of instructions from executable code are implemented on a processor core which in turn outputs event data. A watermark counter inputs event data and counts the number of events that occur within a time period defined by a start and stop signal. The watermark counter outputs a count value, corresponding to the number of events counted in the time period, across a connection to a monitoring computer.
Abstract: The present invention provides a method of forming a metal seed layer 100. The method comprises physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.
Abstract: Profiling operating context. At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to obtain values indicative of a state of an operating context parameter during execution of a traced program on a target processor, and display an indication of a proportion of time during a trace period of the traced program that the target processor operated with the operating context parameter in a particular state.
Abstract: Disclosed herein is a system and method for executing a series of instructions on a circuit. An encoder receives event data corresponding to the executed instructions, wherein the encoder groups the event data into one or more groups and outputs the highest priority event for each group.
Abstract: Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace program that, when executed by a processor, causes the processor to display trace data on a display device (the trace data comprising a plurality of addresses of instructions executed by a target processor), enable a user of the debug-trace program to select an address of the plurality of addresses to create a selected address, and display data based on an operating context proximate in time to when the instruction of the selected address was executed on the target processor.
Abstract: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver Sohm, Brian Cruickshank, Manisha Agarwala, Gary Swoboda
Abstract: A method for manufacturing fully silicided (FUSI) gates and devices, in particular MOSFET devices, is described. The method includes deposition a metal layer over a semiconductor layer of a gate stack, providing a first thermal budget to allow a partial silicidation of the semiconductor layer, selectively removing a remaining unreacted metal layer, and providing a second thermal budget to allow a full silicidation of the semiconductor layer. As a result, the silicide phase can be effectively controlled.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicants:
Interuniversitair Microelektronica Centrum (IMEC), Texas Instruments Inc.
Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
Type:
Application
Filed:
May 12, 2005
Publication date:
November 16, 2006
Applicant:
Texas Instruments Inc.
Inventors:
Juanita DeLoach, Lindsey Hall, Lance Robertson, Jiong-Ping Lu, Donald Miles
Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises valid bit and dirty bit information associated with the caches on different cache levels.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver Sohm, Brian Cruickshank, Gary Swoboda
Abstract: The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.
Type:
Application
Filed:
May 11, 2005
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Asad Haider, Alfred Griffin, Kelly Taylor
Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to determine a difference between the information from caches on different cache levels associated with the common address and to provide the difference to a user of the software.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver Sohm, Brian Cruickshank, Gary Swoboda, Jagadeesh Sankaran, Bradley Caldwell
Abstract: A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit (the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program), a first memory operatively coupled to the processing circuit (the first memory comprising instructions to be executed by the processing circuit), and a memory location operatively coupled to the trace system (the memory location writable by the target program). The trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.
Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.
Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information from the caches is associated with a common address. The processor also provides the information to a user of the software.
Type:
Application
Filed:
May 15, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Oliver Sohm, Brian Cruickshank, Gary Swoboda
Abstract: Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of operating at one or more security levels including a first and a second security level, a memory system coupled to the processor (the memory system stores a first program that executes on the processor at the first security level, and a second program that executes on the processor at the second security level), and a register configured to store an entry point address to the first program (wherein an instruction that executes on the processor at the second security level is blocked from writing values to the register). A transfer of control from the second program to the first program is executed if the register provides the entry point address. The transfer of control is blocked if the entry point address is not provided by the register.
Type:
Application
Filed:
May 14, 2006
Publication date:
November 16, 2006
Applicant:
Texas Instruments Incorporated
Inventors:
Michael Asal, Anthony Lell, Gary Swoboda
Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.