Abstract: A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The second device includes a Reed Solomon (RS) decoder having a RS lock indicator and a Moving Picture Experts Group (MPEG) Protocol Interface (MPI) having a MPI lock indicator, wherein the RS and the MPI lock indicators are monitored. Four different states, defined by the values of the RS and MPI lock indicators, determine whether the data communication system will wait for the RS decoder and the MPI hardware block to resynchronize, whether an intermediate-subset of the channel acquisition algorithm is performed or whether the entire channel acquisition algorithm is performed. The method for resynchronization described herein recovers synchronization within a predetermined time without the layers above the physical link layer having knowledge.

Abstract: The present invention is directed to a material handling system (100) and method (200) for isolating a carrier mechanism (110) from the system. The system (100) comprises a track (103) having a channel (105), a turntable (115), and a carrier mechanism (110) coupled to the track structure via the channel. The system (100) further comprises a maintenance station (125), comprising a stub track (130), wherein the stub track is operably coupled to the track structure (103) via the turntable (115). The maintenance station (125) further comprises a power supply (135) and one or more connectors (140) operable to electrically couple the carrier (110) to the power supply (135). One or more stop blocks (145) are provided which are removably coupled to the stub track (130), wherein the stop blocks each comprise a body (155) having a rod (160) extending therefrom.

Abstract: A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250?, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.

Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

Abstract: Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of implanting a heavy ion species such as Germanium deep into an extension region of a substrate adjacent a channel region of the substrate to form a deep amorphized region, then implanting boron or another such dopant species into an extension region of the substrate adjacent the channel region. The implanted dopant is then preannealed (78) at a low temperature to set the junction depth and doping concentration.

Abstract: Image resizing through resampling by poly-phase filtering with a phase generation from input parameters but with lower resolution of the phase for filter selection. Field and frame mode selection creates initial offsets for alignment. A phase accumulator generates sample addressing with its most significant bits, generates filter selection with its middle bits, and maintains its least significant bits for accuracy.

Abstract: A method for identifying format of a video signal including a raster-synchronizing signal having a timing signal spanning a synch interval and a synch-follower signal level adjacent the synch interval, and a color-related signal, includes the steps: (a) ascertaining (1) first signal level of the color-related signal during the synch interval; (2) synch difference between level of the raster-synchronizing signal during the synch interval and the synch-follower level; and (3) peak excursion for the color-related signal; (b) in any order: (1) if first signal level is greater than a first value, set a first factor at one, else zero; (2) if synch difference is greater than a second value, set a second factor at one, else zero; and (3) if peak excursion is greater than a third value, set a third factor at zero, else one; and (c) employing the factors to identify the format according to predetermined relationships.

Abstract: A method for transmitting light in an image display system includes generating a beam of light from a light source. The beam of light is directed at a first segment of an electronically-switchable filter. A first portion of the beam of light is accepted by the first segment of the electronically-switchable filter, and a second portion of the beam of light is rejected by the first segment of the electronically-switchable filter. The first portion of the light beam is modulated to produce at least a portion of a displayed image. The second portion of the light beam is recycled to redirect the second portion of the light beam at a second segment of the electronically-switchable filter. The second portion of the light beam is accepted by the second segment of the electronically-switchable filter. The second portion of the light beam is modulated to produce at least a portion of the displayed image.

Abstract: An apparatus and method for transmitting and receiving a bit stream. On the transmission side, coded bits (Y.sub.t) and an interleaved version of the coded bits (X.sub.t) are separately modulated and transmitted. On the reception side, a priori output probabilities produced by a probability generator (34) are combined (112) and then input to a SISO decoder (111). Combined a posteriori output probabilities (115) produced by the SISO decoder are split (113) and then fed back to the probability generator.

Abstract: An apparatus includes a blocking N-channel MOS (LDMOS) transistor that prevents current flow when the supply connection is reversed. When connected properly, the body diode conducts to provide a start-up function. A bias generator is employed to enable the low drop-out voltage function, allowing the output voltage to be very close to supply.

Abstract: A system and method for determining an optimal antenna position of a directional antenna in a wireless communication system are described. The optimal antenna position is determined by calculating a steering metric value for possible antenna positions and the antenna position with the highest steering metric value is selected as the optimal antenna position.

Abstract: A capacitively coupled microelectromechanical device and method of operation. The micromechanical device comprises: a semiconductor substrate; a member operable to deflect about a torsion axis to either of at least two states; and a switch driven for selectively connecting the member to a voltage signal. When a logic high signal is stored on the memory capacitor 308, the mirror transistor 310 is turned on, grounding the mirror structure 312. When a logic low signal is stored on the memory capacitor 308, the mirror transistor 310 is turned off, allowing the mirror to float electrically. Mirrors that are tied to a voltage potential, which typically are grounded, are affected by a reset pulse and rotate away from their landed position. When the mirrors have rotated to the opposite side, a bias signal is applied to hold the repositioned mirror in place in the opposite state. Mirrors that electrically are floating do not experience the forces generated by the reset voltage and remain in their previous state.

Abstract: A scheme to provide a spectral view of the signals present at the customer premises equipment by the network operator and includes a digital signal processor (DSP) or other signal processing apparatus integrated into a customer premises equipment (CPE) tuner in which the DSP or other signal processing apparatus is operational to perform a spectral analysis.

Abstract: A material handling system (100) and method (200) for isolating a carrier mechanism (110) from the system. The system (100) comprises a track (103) having a channel (105), a turntable (115), and a carrier mechanism (110) coupled to the track structure via the channel. The system (100) further comprises a maintenance station (125), comprising a stub track (130), wherein the stub track is operably coupled to the track structure (103) via the turntable (115). The maintenance station (125) further comprises a power supply (135) and one or more connectors (140) operable to electrically couple the carrier (110) to the power supply (135). One or more stop blocks (145) are provided which are removably coupled to the stub track (130), wherein the stop blocks each comprise a body (155) having a rod (160) extending therefrom.

Abstract: A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.

Abstract: The pass-gate circuit with backgate pull-up includes: a pass-gate transistor coupled between a first port and a second port; a backgate pull-up transistor coupled between a back gate of the pass-gate transistor and a gate of the pass-gate transistor; a first MOS transistor coupled between a first port and the gate of the pass-gate transistor; and a second MOS transistor coupled between a second port and the gate of the pass-gate transistor.

Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.

Abstract: A current control device for driving LED devices uses a switched-mode current control loop inside of an output intensity low-frequency pulse width modulation (PWM) control loop. This allows separate control of current level (for accurate light wavelength output) and light intensity. The current control device requires only one switch to regulate current level, and no other switches for the intensity control. This allows lower parts count for greater reliability and lower system cost.