Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure tin on the nickel layer, selectively covering areas of the leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said Leadframe intended for bonding wire attachment.

Abstract: Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.

Abstract: A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms of efficiency, etc. The capacitor (100) is fabricated with conductive contacts (162) that allow it to be fused to the device (170) via conductive pads (172) of the device (170). As such, the capacitor (100) and device (170) can be packaged together and valuable semiconductor real estate can be conserved as the capacitor (100) is not formed out of the same substrate as the device (170). The capacitor (100) further includes deep contacts (150, 152) whereon bond pads (180, 182) can be formed that allow electrical connection of the capacitor (100) and device (170) to the outside world.

Abstract: Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a gate structure over the semiconductor substrate, wherein a dopant material is implanted at an angle around the gate structure to form a halo structure in a source/drain region of the substrate and underlying a portion of the gate structure. A trench is formed in the source/drain region of the semiconductor substrate thereby removing at least a portion of the halo structure in the source/drain region. A silicon material layer is then formed in the trench using an epitaxial deposition.

Abstract: A low-noise output buffer for a digital signal is based on an analog amplifier having bandwidth greater than the switching rate of the digital logic signal. A converter circuit converts the digital logic signal to a ramp signal provided as an input to the analog amplifier. The ramp signal has a slope determined by a bias current and an input capacitance of the analog amplifier. The bias current is generated by a bias circuit such that the bias current varies as the input capacitance of the analog amplifier varies due to variations in the manufacturing process. Therefore, the slope of the ramp signal remains substantially constant despite the variations in the manufacturing process. In particular, the slope of the ramp signal is not undesirably steep even when the buffer is made by a worst-case “strong” process.

Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Abstract: A system and method implements optimal task partitioning between a general purpose processor (GPP) and a digital signal processor (DSP) to replace a fixed function ASIC solution with an OMAP software solution to implement a 3G phone that uses OMAP and requires MIDI synthesis, yielding a reduced system cost.

Abstract: A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain signals for optimally combining the receiver chain signals in a composite equalized signal and uses noise-based time-varying postscaling the equalized signal. The receiver determines noise-based scale factors by comparing signal symbols to dispersed replica symbols of a training sequence for the incoming signal.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up mode signal controls electronics associated with one or more amplifiers to facilitate settling time of an output signal of the amplifier(s) that occurs when the gain of the amplifier changes. The gain control signal also can be delayed to provide a delayed version of the gain control signal for controlling gain of the amplifier(s).

Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.

Abstract: A power switching circuit includes a power MOS transistor that has a maximum source-drain voltage substantially higher than a permissible gate-source voltage, and that has a current path connected in series with a load between first and second supply terminals, and comprising a gate driver circuit that drives the gate of the power MOS transistor directly from the supply voltage. A gate driver circuit has a pair of series-connected switching transistors connected between the first and second supply terminals. An interconnection node between the switching transistors is connected to the gate of the power MOS transistor. The gate driver circuit further includes a reference voltage source and a voltage comparator comparing the gate voltage of the power MOS transistor with the reference voltage to provide a disabling output that disables one of the switching transistors when the gate voltage of the power MOS transistor reaches the reference voltage.

Abstract: A motor starter for use with a motor (20) having a main winding (M) and a start winding (S). The starter has a PTC thermistor (30) connected in series with the start winding (S). A triac (40) is connected between PTC thermistor (30) and a power source line. A control circuit (50) is connected to the power source line for providing a voltage for a gate terminal (G) of triac (40) and an overload relay (60) is connected between the power source (10) and the motor (20). The control circuit (50) preferably includes a current detecting circuit (52) for detecting the inrush current and a voltage generating circuit (54) for generating the voltage in response to the detected inrush current. At the startup of motor (20) the control circuit (50) allows triac (40) to turn on by providing the gate terminal (G) with the voltage based on the inrush current. According to this invention, the power consumption of the start winding S after the startup of the motor (20) can be almost zero thus providing low power consumption.

Abstract: The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW processor. The basic approach of these methods is to assign a node n of the dependence graph to the cluster to which it has the strongest affinity. A node n has the strongest affinity to the cluster containing its closest common ancestor node. Then, the mirror image node or nodes of the node n are located if they are present in the graph and are assigned to other clusters in the processor to which they have the strongest affinity.

Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.

Abstract: A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 543), wherein S is greater than one. Each of the sub-units is operable to execute, during an execution cycle, at least one of the instructions in the instruction set in response to at least two data arguments (A, B). The processor further comprises circuitry (58A1, 58A2, 58A3, 58B1, 58B2) for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle.

Abstract: A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter (20) includes digital upconverter functions (36I, 36Q) that operate in combination with a digital band-pass sigma-delta modulator (40) to generate modulated digital signals at a sample frequency that is a multiple of the transmit frequency. The digital band-pass sigma-delta modulator (40) applies a noise transfer function in a feedback filter (72) in which the center of the pass band corresponds to the transmit frequency, and in which notches in the characteristic can be symmetrically or asymmetrically selected to correspond to specific frequencies, such as the receive band frequency, in which transmit noise is to be minimized.

Abstract: A system and method for providing digital compensation and correction for an amplifier. The system is configured to provide a digitally compensated representation of a first amplified analog signal indicative of a first parameter based on a digital representation of the first amplified analog signal and a digital representation of a second analog signal indicative of a second parameter. The digitally compensated representation of the first amplified analog signal is determined by applying a pre-stored compensation factor to an offset adjustment calculation for the second parameter to provide a compensated offset adjustment. The compensated offset adjustment is combined with an adjusted gain to provide an offset and gain correction for weighting the first parameter to provide the digitally compensated representation of the first parameter. The adjusted gain can be determined by applying a pre-stored gain factor data to the second parameter.