Abstract: Determining whether a device is defective by analyzing the sound signals generated by the device. Digital samples are generated to represent the sound signals. Digital samples are transformed from the time domain to the frequency domain to generate a frequency spectrum. By comparing the levels of intensity at a corresponding frequency to the threshold levels of intensity, defective devices can be determined.

Abstract: An expert system that provides an analysis of protocol exchanges and protocol relationships across multiple data units, such as packets, of a network and within data units themselves is described. The system collects a number of facts and based on rules governing the data units, new rules and facts are gained from the analysis. The invention is extensible for additional protocols and diagnostics by updating a knowledge database with dynamic rules for any application or protocol desired.

Abstract: The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

Abstract: A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Abstract: A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product.

Abstract: A display system 100 includes a light source 110 and a color wheel 114. An optical section 112 is arranged to receive light from the light source 110 and to direct the light toward a color wheel 114. A digital micromirror device 122 is arranged to receive the light from the color wheel 114 and to direct image data toward a display. The image data includes an array of pixels arranged in rows and columns. The array of pixels is arranged as curved color bands during a first time period and rectangular color bands during a second time period. The second time period being concurrent with but of a shorter duration than the first time period.

Abstract: A method for packing a semiconductor device 301 in a carrier tape 406 without damage to the leads 302 includes an interlocking mechanism between the molded semiconductor device with indentations 305 formed into the package body, and the carrier tape having mating protrusions 407 slightly smaller than the indentations which cause the device to be held securely without significant movement after a cover tape 409 is adhered to the carrier tape. The features of correctly sized pockets and pedestals, the cover tape, and the interlocking device indentations and tape protrusions prevent damage to the device leads as a result of impact.

Abstract: An integrated circuit having copper interconnecting metallization (311, 312) protected by a first, inorganic overcoat layer (320), portions of the metallization exposed in windows (301, 302) opened through the thickness of the first overcoat layer. A patterned conductive barrier layer (330) is positioned on the exposed portion of the copper metallization and on portions of the first overcoat layer surrounding the window. A bondable metal layer (350, 351) is positioned on the barrier layer; the thickness of this bondable layer is suitable for wire bonding. A second, organic overcoat layer (360) is surrounding the window so that the surface (360a) of this second overcoat layer at the edge of the window is at or above the surface (350a) of the bondable layer. The second overcoat layer may be spaced (370) from the edge of the bondable metal layer.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

Abstract: A method of speech recognition with compensation is provided by modifying HMM models trained on clean speech with cepstral mean normalization. For all speech utterances the MFCC vector is calculated for the clean database. This mean MFCC vector is added to the original models. An estimate of the background noise is determined for a given speech utterance. The model mean vectors adapted to the noise are determined. The mean vector of the noisy data over the noisy speech space is determined and this is removed from model mean vectors adapted to noise to get the target model.

Abstract: A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first transistor of a first conductivity type coupled between a supply voltage node and an upper control voltage node; and a second transistor of a second conductivity type coupled to the upper control voltage node to compensate for process variations in devices of the first conductivity type. Additionally, a target pull-in voltage generator includes circuitry for providing a pull-in control voltage that will always be inside the control voltage window, and also tracks process, voltage supply, and temperature variations.

Abstract: A signal processing device includes a biorthogonal filter bank that processes a finite length signal including a left boundary and a right boundary. The biorthogonal filter bank includes an analysis filter bank. The analysis filter bank includes one or more left boundary filters, one or more right boundary filters, and one or more steady-state analysis filters. Each left boundary filter and each right boundary filter includes a row vector.

Abstract: A single-inductor dual-output buck converter and control method that facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage by selection of respective duty cycles. The topology of the inverter includes a pair of diodes or switches that can selectively re-circulate inductor current. The converter is generally operated at a fixed frequency with four stages of operation. A first and third stage of operation provide power to a first and second output, respectively. A second and fourth stage of operation re-circulate inductor current and can partially recharge a battery type power source. The power output for each stage (voltage and current) can be selectively obtained by computing and employing appropriate time periods for the stages of operation that correspond to appropriate duty cycles.

Abstract: The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

Abstract: A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation.

Abstract: Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +VS, the level shifter provides a voltage to the input resistor that ramps up from ?VS to 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to ?VS, thereby providing a negative output supply voltage ?VS with a slew rate that linearly tracks the slew rate of the master positive output supply.

Abstract: An apparatus for controlling operation of an amplifier device when supply voltage provided to the amplifier device varies at an input voltage supply locus. The amplifier device has an operating parameter varying in generally direct proportion with the supply voltage. The apparatus includes: (a) a reference parameter supply providing a reference parameter; (b) a modeling circuit coupled with the input voltage supply locus that models the amplifier device; (c) a comparing circuit coupled with the modeling circuit and the reference parameter supply that compares a model operating parameter from the modeling circuit and the reference parameter and provides a control signal to the modeling circuit and the amplifier device in response to the comparing; the control signal alters operation of the modeling circuit and the amplifier device to reduce variance between the reference parameter and the model operating parameter from a predetermined relationship.

Abstract: A technique for implementing impedance matching circuits 100 that use the transfer functions of each line impedance model. This technique allows implementation of an impedance match for a diverse number of line impedances reusing the same circuit 100 topology, by simply adjusting coefficients to accommodate different line impedances.

Abstract: The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles (320) having a given beam divergence, and forming a diverged beam of charged particles (360) by subjecting the beam of charged particles (320) to an energy field (350), thereby causing the beam of charged particles (320) to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles (360) into the substrate (330).