Abstract: A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed. A set of available code word lengths and code rates are to be supported by the transceiver. These available code word lengths and code rates are implemented as a subset of starting code word lengths, which are length-reduced by shortening and puncturing selected bit positions in the starting code word length to attain the desired one of the available code word lengths and code rates. The bit positions to be shortened and punctured are selected in a manner that avoids interference between the shortened and punctured bit positions, and that attains excellent code performance.

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (?1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (?2).

Abstract: An integrated circuit package lead frame, comprising a plurality of leads and a spine electrically connected to said plurality of leads, said spine comprising indentations between a pair of said leads. The indentations prevent the pair of leads from becoming electrically connected to each other after a singulation process.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming an L-shaped spacer (410) proximate a sidewall of a gate structure (130) located over a substrate (110), and implanting halo/pocket implant regions (620) through the L-shaped spacer (410) and in the substrate (110).

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).

Abstract: A graphametric equalizer has graphic and parametric equalization capabilities within a single non-redundant system. A translation function capability converts user selected inputs for center frequency, bandwidth and gain into allpass filter parameters to realize an allpass filter-based equalization filter structure capable of performing graphic and/or parametric equalization on-the-fly. The graphametric equalizer has a softening function capability to time user inputs and increment filter parameters gracefully such that the graphametric equalizer can be recharacterized with new filter parameters on-the-fly without incurring undesirable audible artifacts.

Abstract: A flip chip semiconductor device having non-solder contact terminals is assembled by securing the chip and substrate with a rapidly thermosetting adhesive. The process is amenable to various bump and substrate materials, and has the advantage of simultaneously adhering the components and of providing a void free underfill. The process makes use of absorption of infrared energy by the chip to heat the adhesive and cause it to flow prior to rapidly solidifying from the center outwardly. The rapid assembly, using a simple infrared exposure apparatus is compatible with reel to reel, or other highly automated in-line processes.

Abstract: The preferred embodiments of the present invention provide non-invasive approaches of testing ICs that use photon emission from semiconductor devices to provide results of various testing procedures. For example, instead of reading the results from the built-in-self-test (BIST) circuitry using micro-mechanical probes, the results from BIST may be represented using an array of circuit elements configured to emit photons. Accordingly, by reading the photon emission of this BIST circuitry, the results of the testing procedures may be measured non-invasively. In addition, the preferred embodiments also may use an external light source to initiate on-chip testing functions so that the number of external connections to the IC may be further minimized. For example, instead of providing input signals to BIST circuitry using micro-mechanical probes, pulsed lasers may provide desired input signals.

Abstract: Contention communications often requires a station to wait an inordinate amount of time before the station is able to transmit its data successfully. In many applications, an extended delay is not acceptable. Contention-free communications in a contention period allows a hybrid coordinator (HC) to schedule contention-free access to a communications medium so that extended delays may be eliminated, and to coordinate contention access to the medium so that better throughput and delay performance is achieved. A method for creating contention-free communications within a contention communications period is presented, along with adaptive algorithms for contention access during the same contention period.

Abstract: A package is disclosed, which includes a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal traces are formed. The solder mask covers at least a portion of the surface of the substrate. And the first aperture through the solder mask exposes a plurality of the metal traces.

Abstract: The status of execution of jobs (used to characterize cells) is notified asynchronously. As a result, the processing and network resources may be optimally used. In an embodiment, a flow controller divides an entire characterization task into multiple jobs, and schedules each job for execution on one of several client machines. The client machine sends a notification asynchronously after completion of execution of the job. In an embodiment, the asynchronous communication is implemented using socket interface on top of TCP/IP protocol.

Abstract: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EOM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Abstract: A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals SA–SH, and top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm that represent the top envelope waveforms and bottom envelope waveforms of RF signals output from an optical detector. An analog/digital conversion unit (26) converts analog top envelope signals SAtop–SHtop and bottom envelope signals SAbtm–SHbtm corresponding to all input RF signals SA–SH to digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm, respectively. A digital operation unit (28) performs digital operation treatment for digital top envelope signals QAtop–QHtop and bottom envelope signals QAbtm–QHbtm to generate various servo error signals.

Abstract: A high speed Bluetooth system with switch-to quadrature amplitude modulation allows for simple mobile devices with video data rates in applications such as Internet downloading. Mobile devices may have multiple antennas and adaptive hopping frequencies.

Abstract: An audio loudness compensation system includes a level sensor receiving an audio input signal and operable to estimate a level of the audio input signal over a first predetermined time period, and a level mapper receiving the estimated level and operable to map the estimated level to a raw audio gain in response to a slope setting and an offset setting. The system further includes an attack and decay filter receiving the raw audio gain and operable to smooth out increasing and decreasing changes in the raw audio gain in response to a second and, possibly a third predetermined time period, and a compensation filter receiving the smoothed raw audio gain and operable to modify the audio input signal in response to the smoothed raw audio gain, a center frequency setting and a bandwidth setting, and generate a loudness compensated audio output signal.

Abstract: Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.

Abstract: A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.

Abstract: An improvement to a Novellus HDP SPEED reactor chamber is described. An evacuation port of the Novellus SPEED Chamber is at one location in the chamber to remove injected cleaning gas from the chamber and there is a single input for cleaning gas connection into the chamber. In accordance an improvement a plurality of clean gas injectors is positioned on an adapter in the chamber and connected to the single input gas connection for distributing the cleaning gas in the chamber with the injectors spaced away from the evacuation port. The adapter is a U-shaped adapter and is positioned in the chamber with the adapter connected at the base to the single input gas connection. The adapter has two semicircular branch legs extending in opposite directions about the chamber to free ends that are connected to gas injectors. The free ends with the injectors are located in the chamber almost on the opposite end of the chamber from the evacuation port.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.