Abstract: A state machine for attenuating the transition into and out of NLP state to reduce voice clipping and to reduce echo leak in a voice over packet signal transmission. The state machine interposes two additional transitional states between the NLP active state and the NLP inactive state to eliminate the sharp transition of NLP activity. An NLP entering state is used to gradually reduce the mixing ratio of echo and voice to attenuate the transition from passage of echo in the NLP inactive state to the suppression of echo in the NLP active state. An NLP exiting state is used to gradually increase (ramping the change) the mixing ratio of echo and voice to attenuate the transition from suppression of echo in the NLP active state to passage of echo in the NLP inactive state.

Abstract: A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining whether the parameter exceeds a reference value, and as long as the parameter exceeds the reference value, repetitively blowing fuses associated with binarily weighted trim elements of the first trim array to eliminate trim contributions thereof to thereby decrease the parameter by weighted amounts corresponding to a present trim array bit number value until either all fuses of the first trim array have been blown or enough have been blown to cause the parameter to be less than a ?LSB/2 weight. If the parameter then is less than the ?LSB/2 weight, a fuse of the second trim array corresponding to a present bit number is blown to increase the parameter to greater than a +LSB/2 weight. The procedure is repeated until all fuses in one trim array have been blown, to thereby minimize the number of residual trim elements.

Abstract: An integrated circuit functionality test determining shorts between adjacent pins of all the IC pins while simultaneously determining pin continuity in only three steps. The process includes categorizing all pins of the IC into three sets of pins. One set of pins is connected to digital instruments, a second set of pins is connected to 0 volts, and a third set of pins is left open. The digital instruments sink current in parallel from the first set of pins to identify any shorts of the first set of pins. The process is repeated for each of the other two sets of pins. For IC packages having double and quad terminal positions, each terminal position is treated like a single terminal position, and the measurements of the respective sets of pins of each terminal position is measured in parallel.

Abstract: For use with a multiple-input, multiple-output (MIMO) transmitter, a signal field controller, a method of controlling signal fields and a MIMO transmitter incorporating the controller or the method. In one embodiment, the controller includes: (1) a primary signal field mode indicator configured to cause a primary signal field to indicate a presence of a supplemental signal field and provide the primary signal field to the MIMO transmitter for transmission thereby and (2) a supplemental signal field generator coupled to the primary signal field mode indicator and configured to provide a supplemental signal field to the MIMO transmitter for further transmission thereby only when the primary signal field indicates the presence.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

Abstract: A probe, listen and select (PLS) technique can be used to select from an available frequency spectrum a frequency band whose communication quality is suitable for wireless communication at a desired rate. Probe packets can be transmitted on different frequencies (223) during a known period of time (TPLS), and frequency channel quality information can be obtained (225) from the probe packets. This quality information can then be used to select a desirable frequency band (227). The communication quality of the selected band can also be used as basis for selecting (141) from among a plurality of modulation and coding combinations that are available for use in communications operations.

Abstract: A device and method for providing real time compensation for packet loss in the transmission of facsimile data over packet networks to avoid the generation of page loss data and the termination of facsimile transmission. Facsimile devices have a low tolerance for interruptions in transmission. Packet networks commonly have a transmission interruption rate above the tolerance of facsimile equipment. In order to compensate for transmission interruption, the present invention teaches the buffering of facsimile data by scan line at the receiving end, the evaluation of buffered scan lines for packet loss and the discarding of scan lines having packet loss to conceal the packet loss from the receiving facsimile equipment to avoid detection of page errors by the receiving facsimile equipment which could cause loss of facsimile transmission.

Abstract: An occupant weight sensor (1) for placement between a frame (7) fixed to the chassis of a vehicle and a second frame (8) supporting a vehicle seat has a sense element having a first body (12, 22, 28, 34, 50, 62, 64, 68, 84) formed with a planar sense surface on which are mounted piezoresistors electrically connected in a Wheatstone bridge configuration. A post (12a, 22c, 28c, 34e, 50b, 62a, 64a, 68b, 84g) extends outwardly from the first body for attachment to the first frame. A second body is formed with a force transfer portion (14a, 24g, 30d, 36b, 52a, 70a, 94a) permanently attached to the first body along an outer periphery circumscribing the sense surface. The piezoresistors are electrically connected to conditioning electronics received in a chamber formed between the two bodies. The effects of parasitic loads on the sense element are minimized by selected placement of the piezoresistors on the sense surface.

Abstract: A system and method are disclosed to mitigate the interference on DSL due to high frequency components associated with a change in a POTS condition, such as POTS ringing. In response to detecting that a potentially disruptive POTS condition is to about to occur, downstream DSL traffic can be temporarily stopped. The stoppage can include downstream traffic of voice and/or data.

Abstract: A torsional hinged mirror design with reduced flexing. In addition to a central spine to prevent or reduce flexing of the tips, the mirror layer also includes perimeter ridges to reduce or prevent flexing or warping of the mirror edges. To provide an even stiffer mirror with minimum weight, either or both of the hinge plate and balancing plate may also include perimeter ridges that align with the perimeter ridges of the mirror layer.

Abstract: The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.

Abstract: The present invention provides a channel estimate enhancer for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas, where N is at least two. In one embodiment, the channel estimate enhancer includes a first preamble generator that produces a basic preamble configured to provide gain training and channel estimation sequences to one of the N transmit antennas during initial time intervals. Additionally, the channel estimate enhancer also includes a second preamble generator, coupled to the first preamble generator, that produces supplementary preambles configured to provide a set of gain enhancing channel estimation sequences to each of (N?1) remaining transmit antennas during (N?1) corresponding sets of subsequent time intervals.

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract: The present invention provides, in one embodiment, a method of forming an opening in a dielectric layer 150. In this embodiment, the method comprises forming a dielectric layer 150 over a target layer 130 located over a microelectronic substrate 110 and subjecting the dielectric layer 150 to a plasma etch 165 to form an opening 145 in the dielectric layer 150, wherein the plasma etch 165 is highly selective to the target layer 130, such that a selectivity of the dielectric layer 150 to the target layer 130 is at least about 18:1 and a dielectric etch rate of the plasma etch 165 is at least about 380 nm/min.

Abstract: A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a plurality of audio amplifier channels (22), each of which includes a pulse-code-modulation (PCM) to pulse-width-modulation (PWM) conversion function (25), which generates PWM signals for application to the plurality of power stages (22). The audio amplifier channels (20) each also include an interchannel delay function (28) for delaying the PWM edges relative to other channels (20), for reducing noise. The audio amplifier channels (20) each also include delay adjust circuitry (32) for gradually increasing and decreasing the interchannel delay of the channel (20) on startup and shutdown. This permits a single control terminal (VALID) at the processor to globally enable and disable all of the power stages (22).

Abstract: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode 200, and integrated circuit 800 have includes a semiconductor device 805 having the described source/drain electrodes 810.

Abstract: In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixe

Abstract: A flexible carrier tape system suitable for transporting and/or storing an electrical component, which has an exposed metal surface sensitive to corrosion. The system comprises a container having a corrosion inhibitor therein, which is capable of reacting with the metal to form a film as an electromechanical barrier against corrosive attack; a component is placed in the container. In the preferred embodiment of the flexible carrier tape system, an elongated base strip has an upper surface and a plurality of longitudinally spaced cavities extending downwardly a predetermined depth from said upper surface for housing electrical components therein. A component in each of the cavities has at least one exposed metal surface sensitive to corrosion. An elongated cover strip for the upper base strip surface has a corrosion inhibitor deposited on that strip surface which faces the cavities.

Abstract: Modularized clock decoupling and signal delay management is provided for the purpose of reducing simultaneous binary signal switch-induced inductive voltage transients in lower voltage synchronous semiconductor devices. The voltage levels in low-voltage devices must be tightly maintained for proper transistor logic operations. Signal switching results in current changes on the power net of an IC. Current changes produce inductive voltage transients which propagate throughout the device and which can interfere with signal transmission and device operation. Relatively independent functioning circuits of an integrated circuit are isolated from the chip clock and each isolated circuit module is provided with its own independent, same-frequency, but slightly out-of-phase clock signal. Signal switching within any module is thus occurring out-of-phase with that of all other modules and, as a result, switch-associated voltage transients are limited to those associated with one module's circuits at a time.