Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element×the time period of the serial clock), wherein ‘×’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.

Abstract: A method for detecting a boundary between two sequences in a wireless local area network is presented that permits rapid detection of the boundary. The method includes provisions for proper operation when significant interference and multi-path can degrade the received transmission significantly. Additionally, when a modification is made to the signaling format to signal a special enhanced mode with performance and features above those that are specified in a single technical standard, the method detects the boundary between sequences regardless of whether they have the standard format or the modified format.

Abstract: An integrating rod (200) for use with a multiple segment dynamic filter, such as a spiral dichroic color wheel having three or more narrow filters adjacent to the exit face (206) to enable the integrating rod to recapture light rejected by a given segment of the dynamic filter. The rejected light travels back through the integrating rod where a majority of the light strikes the mirrored entrance face (202). Light reflected by the mirrored entrance face, or light exiting through the entrance aperture (204) and returning to the integrating rod after being reflected by the lamp reflector, once again travels to the exit face (206) of the integrating rod (200). After exiting through the exit face (206) of the integrating rod (200) a second time, the recycled light has a good chance of striking a different filter segment of the dynamic filter and being used by the display system.

Abstract: A software system is provided that tracks employee and contractor operation/certification of fabrication equipment and processes is provided to ensure that only qualified personnel are allowed to process the materials. The system is real time with an auto-update features, Web enabled, dynamic tool interface with automatic record checking and reporting.

Abstract: A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate broken die lands or other malfunctions.

Abstract: A retract circuit (40) for retracting a data transducer carriage assembly (17) of a mass data storage device (10) to a retracted position has a digital state machine (55) that is user programmable to operate in a selected retract mode. An analog control circuit (44) is provided for receiving control signals from the digital state machine (55) for providing analog retract signals to move the data transducer carriage assembly (70). The digital state machine (55) is user programmable to operate in constant voltage, velocity detect, float and pulse, and crash stop detect modes. Preferably, the digital state machine (55) is programmed to detect a velocity of the data transducer carriage assembly (17). The digital state machine (55) also is preferably programmed to detect an error velocity of the data transducer carriage assembly (17) from a difference of a measured voltage across the data transducer driver (22) from a predetermined voltage.

Abstract: The invention relates to a software system and method for dynamically varying context sensitive menus of a software system. In this method, a menu item is added to a context sensitive menu of a graphical user interface (GUI) at the request of a subsystem module. Then, an activation event for the context sensitive menu is received from the GUI. The added menu item is displayed as either active or inactive based on a response to a query from the software system to a second subsystem module. The action associated with the menu item specified by the first subsystem module is executed when the menu item is selected only if it is active.

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: The present invention provides a synchronizer for use with a multiple-input, multiple-output (MIMO) transceiver employing multiple individual transceivers. In one embodiment, the synchronizer includes a synthesizing unit coupled to a reference oscillator and configured to generate separately synthesized radio frequency (RF) signals having relative phase differences. Additionally, the synchronizer also includes a synchronizing unit coupled to the synthesizer unit and configured to adjust the relative phase differences of the separately synthesized RF signals to be less than a predetermined difference to provide synchronization of the multiple individual transceivers based on the predetermined difference.

Abstract: A location system for locating a parked vehicle, a method for providing a location of a parked vehicle and a personal wireless device including the location system or method. In one embodiment, the personal wireless device includes (1) a positioning system, (2) a user interface and (3) a parked vehicle location system coupled to the positioning system and the user interface. The parked vehicle location system includes (3A) a parking determiner configured to automatically ascertain and store at least one parking event of a vehicle associated with the personal wireless device and (3B) a parking event retriever, coupled to the parking determiner, configured to present the at least one stored parking event.

Abstract: An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller.

Abstract: A print method converts page description data specifying a print document into pixel data. The print system includes a central processing unit, a first memory and a second memory that is smaller but faster than the first memory. The method extracts a display list from the page description data (503), allocates space within the first memory to serve as a page buffer and divides the page buffer within the first memory into a plurality of sub-bands. Each sub-band is smaller than the second memory. For each sub-band the method renders pixels of a current sub-band into the second memory (506). When the sub-band is completely rendered, the method transfers pixel data from the second memory to the current sub-band of the page buffer (509). When all sub-bands are rendered, the page is printed by transfer of data from the page buffer to a print engine (512). The central processing unit and the second memory are preferably disposed on the same integrated circuit.

Abstract: An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes (22,24) occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits (70, 80, 90) are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as “010” and “101”. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.