Abstract: A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register.

Abstract: A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one or more logic elements within the integrated circuit are set to one or more selected values. The selected values produce a minimum leakage current associated with the integrated circuit when the integrated circuit is operating in a standby mode.

Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.

Abstract: The present invention provides a solution for interleaving data frames, in a digital subscriber line system in which the data frames are divided into first and second codewords such that the first codeword comprises an even number of data bytes and the second codeword comprises an odd number of data bytes. With an interleaver depth (D) greater than a number of data bytes in the codewords (N), the codewords are written to a first matrix (51) in a predetermined manner (220), and read from the first matrix (51) in a predetermined manner (240 or 250) in which the data bytes of the codewords are delayed by a number of bytes. The codeword data bytes (defined by: B0, B1, . . . , BN−1) are delayed by an amount that varies linearly with a byte index, where byte Bi (with index i) is delayed by (D−1)×i bytes. Further, de-interleaving the interleaved data frames can be implemented by a reverse interleaving writing (340 or 350) and reading (320) in a second matrix (52).

Abstract: A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

Abstract: A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused into a first metal.

Abstract: A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating photoconductive layer (270) coupling the semiconductor features (230, 235, 240, 260). The photoconductive layer (270) is configured to provide conductivity between the semiconductor features (230, 235, 240, 260) in a presence of a plasma.

Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

Abstract: A apparatus for controlling an actuator including, an integrator circuit to generate an integrated signal to be represented by a back EMF voltage, a amount circuit to generate a amount signal to indicate the amount to raise or lower the integrated voltage, a direction circuit to generate a direction signal to raise or lower the back EMF voltage, a comparator circuit to compare said integrated voltage with the back EMF voltage, and a switch circuit to add and subtract the amount signal with the integrated voltage in accordance with the direction signal.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).

Abstract: A motor speed resolution enhancement method and system. A display system controller (202) measures the frame rate of an incoming signal to determine the desired color wheel speed. A digital speed control word (212) representing the desired color wheel speed is written to the motor control circuit (204). The motor control circuit uses the digital speed control word (212) to generate analog control voltages (214) that drive the motor (206). The motor controller (204) also detects the position of the motor and generates a series of commutation interrupts (216). The display system controller 202 accurately measures the input signal's frame rate to determine the proper rate at which to spin the color wheel. The resulting desired speed word has a higher resolution than the motor control circuit (204) is able to receive. The disclosed invention provides a method of increasing the resolution of the digital speed control word (212) without upgrading the resolution of the motor control circuit (204).

Abstract: An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The invention eliminates the need for expensive RF test equipment, permitting the use of low cost test equipment to test an integrated RF transmitter. In addition, test time spent to verify the power levels and frequency ranges of a tested transmitter is reduced, further reducing testing costs. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level.

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: Encoder circuitry (39) for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry (39) takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry (39) includes a cyclic multiply unit (88), which includes a circular shift unit (104) for shifting a portion of the information word according to shift values stored in a shift value memory (82) for the matrix entry, and a bitwise exclusive-OR function (106) for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry (92, 96) for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry (39).

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have non-volatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.

Abstract: The present invention achieves technical advantages as a circuit (10) detecting excess current on a servo driver IC and preventing the disruptive damage which can be caused by the excess current. Typically, an isolation (Iso) FET 12 is part of the servo driver IC. The detection circuitry (10) has a sensing FET (14) having only a small silicon area whereby the detection circuit (10) is independent of the Iso FET current (Icc) path, being in parallel rather than in series. The detection circuitry also allows production tests on much smaller current thresholds.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.

Abstract: A method to more accurately monitor remaining battery life under varying load conditions. The measured battery voltage is adjusted for the current load and then used to determine the remaining battery life according to the battery voltage discharge curve for the battery type and chemistry. Advantageously, in an embodiment the present invention the remaining battery life can be determined despite fluctuations in the current due to a changing load and without monitoring current flow so that the determination of battery life is independent of the battery charging process.