Abstract: A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.

Abstract: An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad.

Abstract: A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.

Abstract: A delta sigma modulator circuit sums an input signal with a feedback signal representing signal conditions in a group of integrators to provide an input to a quantizer and monitors a signal at the quantizer output to produce a restore signal (RESETA) indicating an instability condition. An integrator includes a dual purpose switch (S3) that is operated together with first and second sampling switches to accomplish an input signal sampling operation and also is operated together with first and second charge transfer switches and an output reset switch to accomplish precise resetting of the integrator, without being directly connected to the amplifier inputs. The dual purpose switch and the reset switch are controlled, respectively, by performing a logical ORing of a first clock signal and the restore signal (RESETA) and by performing a logical ANDing of a non-overlapping second clock signal and the restore signal (RESETA).

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70), a plurality of pads (100) centrally disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) adhered to the second surface (84) of the substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the openings (86) to adhere the chip (50) to the substrate (70) and surrounding the wire bonding (80), is disclosed.

Abstract: A circuit is provided that can provide, in a single package, a circuit to monitor a sensing element which uses a variable resistor. The circuit (also known as a signal conditioning circuit) may contain resistor input terminals to which a reference set resistor and a resistive sensor can be attached. A reference voltage signal can be applied to both terminals. There are also a circuit for sensing the resulting current flowing through both the set resistor and the resistive sensor. The difference of the currents flowing through each element can then be monitored as being indicative of the difference in resistance between the set resistor and the resistive sensor. The current difference signal can be used to generate a voltage difference signal indicative of the difference in resistance between the set resistor and the resistive sensor. The signal conditioning circuit may be used to adjust the temperature of various devices.

Abstract: A circuit model (50) for use in analyzing a VCM circuit has a first resistor (62), a first inductor (64), a second inductor (58), and a voltage source (60), in series modeling, respectively, a VCM inductor, a winding leakage inductance of the VCM inductor, a VCM inductor resistance, and a BEMF voltage generated across the VCM inductor when the input nodes are open circuited. An input capacitor (56) interconnects the input terminals (52,54) to model an equivalent capacitance of the VCM inductor. Third and fourth inductors (32,34) and a second resistor (36) are connected in a first series loop (28) inductively coupled to the second inductor (58) to model, respectively, an inductance of the top VCM magnet plate, the leakage inductance of the top VCM magnet plate, and a resistance of the top VCM magnet plate.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: An apparatus receives an indicating signal representing a parameter at a monitoring locus and includes: (a) A first measuring unit having a first input coupled for selectively receiving the indicating signal and presenting a first output signal that includes a first monitoring signal representing change in the indicating signal during a first time interval and a first benchmark signal indicating change imparted to signals by the first measuring unit. (b) A second measuring unit having a second input coupled for selectively receiving the indicating signal and presenting a second output signal that includes a second monitoring signal representing change in the indicating signal during a second time interval and a second benchmark signal indicating change imparted to signals by the second measuring unit. (c) An accumulating and indicator unit coupled for receiving and evaluating the first and second output signals and generating an indicator signal that represents the evaluating.

Abstract: A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages) is defined within an address space of a back-up memory associated with the cache and write allocation in the cache is defined on a page basis. Each TLB has a set of entries that correspond to pages of address space and each entry provides a write allocate attribute (550) for the associated page of address space. During operation of the system, software programs are executed and memory transactions are performed. A write allocate attribute signal (550) is provided with each write transaction request. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request.

Abstract: According to one embodiment of the present invention, a method for electroplating electronic devices is disclosed which includes placing the outer surface of a substrate in contact with a solution comprising a conductive material. An electrical current is passed through the solution and the substrate so as to cause the conductive material to deposit on the substrate under the electromotive force caused by the electrical current. The level of the electrical current is varied from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate. The second current level provides a relaxation period to allow the conductive material deposited on the substrate to come to equilibrium.

Abstract: A system and method for generating a message integrity code, MIC, for a MAC protocol data unit in a wireless local area network, WLAN, operating according to the IEEE 802.11 standard. A MAC service data unit, MSDU, sequence control sequence number, SN, input to the MIC algorithm is suppressed, e.g. set to all zeros, when calculating the MIC. Only the fragment number, FN, portion of the sequence control is included in calculation of the MIC. The MIC may therefore be calculated before an actual SN has been determined. All MPDUs include sequential packet numbers, PNs. A station receiving MPDUs checks the PNs of MPDUs having the same SN, and rejects messages which do not have a proper sequential set of PNs.

Abstract: A method for optical digital signal processing, comprises configuring a plurality of binary mirrors to allow a subset of the binary mirrors to represent a range of values. The plurality of binary mirrors comprise a digital micromirror device. Light from a light source is received at the digital micromirror device. The intensity of the light is altered to represent one of the values based, at least in part, on the configuration of the subset of the binary mirrors. The altered light is transmitted from the digital micromirror device to a detector array.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: A method for converting sample rates includes obtaining coefficients from a sample rate conversion coefficient table. In this method, the table is generated prior to the real-time sample rate conversion using LaGrange Interpolation based on the ratio of the input sample rate to the output sample rate.

Abstract: A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal end and is formed with a flat end wall having an aperture aligned with the sensor. A portion of a flexible circuit assembly is bonded to the flat end wall with a connector disposed over the support member. A tubular outer housing is fitted over the several components and its bottom portion is welded to the port fitting while its top portion places a selected load on an O-ring received about the connector as well as internal components of the transducer. In one embodiment, a loading washer (72a) is disposed over the O-ring on a first portion (70a) of a two portion connector (70) and retained by a second connector portion (70b). Protrusions (76a1) formed on the tubular housing (76) pass through cut-outs in the second connector portion to place a load on the loading washer.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A modem comprises circuitry for receiving an analog signal from a line and circuitry for converting the analog signal to a digital signal. The digital signal comprises a plurality of ideal sample points (P0-P3), each separated in time by a period T, and the plurality of ideal sample points comprises a sync sequence (14). The modem further comprises circuitry (34) for detecting the sequence comprising an integer number S of sampling circuits (38, 40), wherein S is two or greater. Each of the sampling circuits comprises circuitry for taking a sample corresponding to each of the plurality of ideal sample points at least once per the period T. Each of the sampling circuits also comprises circuitry for comparing a plurality of taken samples to a correlation sequence. Finally, each of the sampling circuits comprises circuitry for outputting a sync detected signal (SYNC0, SYNC1) in response to a sufficient match between the plurality of taken samples and the correlation sequence.