Abstract: A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme bus voltages; enabling/disabling circuits (315, 316) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups (320) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Abstract: An ASIC (14, 14′, 14″) conditions two independent outputs (VINM, VINP) of a full Wheatstone piezoresistive bridge (12) in separate conditioning paths. Each path is provided with a bridge supply voltage (VHB1, VHB2) which can serve as a temperature related input signal to respective offset and gain compensation control circuits. The half bridge outputs are inputted to respective amplifiers (U1, U2) along with a selected percentage of the temperature dependent bridge supply voltage. The outputs of the amplifiers provide a signal proportional to respective half bridge output voltage. In one embodiment, the output of the amplifier (U2) in one conditioning path of one half bridge is connected to the input of an amplifier (U4) in the other conditioning path to provide a signal in the one path proportional to the Wheatstone bridge differential output voltage and in the other path a signal proportional to the Wheatstone half bridge output voltage.

Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Abstract: A maximum length (M) of compressed codes desired to be decoded in a single lookup is determined. 2M rows are generated, with each row having a bit indicating whether a corresponding M-bit combination, when viewed from the first bit, contains a compression code and a source code corresponding to the compression code. A matching row corresponding to a value represented by M-bits of a source bit stream (“present portion”) is first determined, and the source code in the matching row is set as the decoded value if the matching row is indicated to contain a compression code. If the length (P) of the compression code corresponding to the decoded value is less than M, the last (M−P) bits of the present portion are used as a part of the next portion. Additional bits are used to generate the decoded value if the present portion does not contain the entire compression code.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: A shift register with low power consumption has memory circuits 151-15N connected in series, gate circuits in memory circuits 152n−1 in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits 152n in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Data is loaded into various of lines (506) in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag (1236) associated with the data line is set to a valid state (526). In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields (520, 522) in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache.

Abstract: A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.

Abstract: In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

Abstract: A method and system for mask pattern correction are disclosed. A portion of a mask pattern is segmented into segments (22) that include a base segment (22a) and a relational segment (22b). The relational segment (22b) is matched with the base segment (22a). A proximity correction is determined for the base segment (22a), and a critical dimension correction is determined for the relational segment (22b). The critical dimension correction is determined with respect to the proximity correction of the matching base segment (22a).

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: An analog-to-digital converter (10) includes a high order delta sigma modulator followed by a decimation filter. A monitor circuit (104)coupled to the output of the delta sigma modulator operates to reset its integrators if an unstable condition is detected on the output. The monitor circuit produces first and second jamming signals in response to either a detected overvoltage or undervoltage of the delta sigma modulator input. A logic circuit (SW1) includes a data input coupled to the output of the delta sigma modulator and a data output (89) that jams the input of digital filter (106) with “1” s or “0” s in response to the first or second jamming signal, respectively, to ensure a correct (+) or (−) full scale decimation filter output.

Abstract: A low power scan architecture is formed of a conventional scan architecture. The conventional scan path is divided into equal parts and each part is operated in sequence. An adaptor receives the conventional shift and capture control siqnals from a conventional tester and provides separate shift and capture control siqnals for each of the scan path parts. The adaptor also receives additional select control siqnals from the tester for selecting operation of individual ones of the scan path parts. The disclosed architecture reduces power consumption during testing by a fraction representing the number of equal parts, while maintaining the same test time.

Abstract: The failure rate of an integrated circuit (IC) is quickly determined by analyzing the corresponding design. The IC is partitioned into multiple cells, with each cell typically containing a logic gate. A default input signal is assumed for each cell and the default failure in time (FIT) rates of the cells are computed. The default signal is selected based on pessimistic assumptions on overshoots. The IC is analyzed to determine the cells (“overshoot cells”) that would actually experience overshoots. Detailed analysis is performed on the overshoot cells to determine exact FIT rates. The failure rate of the IC is determined based on the exact FIT rates for the overshoot cells and the default FIT rates for the remaining cells.

Abstract: A method for preconditioning a CMP polishing pad and retaining ring prior to semiconductor wafer polishing. In the method of the present invention, the retaining ring is lowered to contact the rotating polishing pad, and a cleaning chemistry of ammonium citrate is applied to the pad. In an alternative embodiment, the cleaning chemistry comprises an aqueous solution of ammonium citrate, and a surfactant and/or copper inhibitor. After a sustained preconditioning period in which the retaining ring and polishing pad are polished, the pad is rinsed, lowering particulate buildup on the pad between wafer polishing steps, and bringing defect levels into an equilibrium state prior to each wafer polishing step.

Abstract: A drop-in aperture 20, which improves the performance and lowers the cost of electro-optical SLM packages. The disclosed package provides a separate metal light shield (aperture) 20 and antireflective coated cover 33, and positions the aperture 20 inside the package 40 in close proximity to the SLM's 41 surface. This approach further uses an on-chip SLM light shield to define the projected screen border, thereby making the edge definition of the metal drop-in aperture less critical. Therefore, the cover can be mounted well away from the plane of the SLM, which relaxes the defect requirements of the cover and lowers the cost of the overall package. The package of this invention improves the performance and lifetime and lowers the cost of projection display systems.

Abstract: Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.

Abstract: A substrate (300) for use in semiconductor devices, having first (301a) and second (301b) surfaces and a base structure including insulating material. A plurality of I/O terminal pads (302, 303) is distributed on the first and second surfaces, respectively, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers (304 to 309) is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer (304 or 307, respectively) opposite each of the surfaces has openings (320a, 320b) therein configured so that the metal areas (307a) directly opposite each of the terminal pads (303) are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals (303) and the remainder of the metal layer (307).

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal path includes a memory circuit (121C, 127C). The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.