Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: Systems and methods are provided for calibration of a transmitter system modulator, wherein local oscillator nodes of a mixer are held at first and second voltages, and a first offset value is determined. The terminals are then held at third and fourth voltages and a second offset value is determined. The first and second offset values are then averaged to provide a calibration offset value for the modulator.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: Apparatus and method for assembling a semiconductor device on a wiring substrate is disclosed, wherein Pb (lead) is not used and the chance of generation of defects is reduced. Semiconductor package (100) has solder balls (114) containing Sn (tin), Ag (silver) and Cu (copper). Wiring substrate 200 has connecting terminals 208 for connecting solder balls (114). The connecting terminals (208) have an Au (gold) layer (212) and a Ni layer (210). In the operation for assembling semiconductor package (100) onto wiring substrate (200), because solder balls (114) are heated and fixed on connecting terminals (208), Au in Au layer (212) diffuses into balls (114). Because Au is contained in solder balls (114), a high bonding strength is obtained, and the chance of generation of defects is reduced.

Abstract: A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

Abstract: The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core 12 of this SVP (Scan-line Video Processor) 10 is made up of a three layer construction of the data input register (DIR) 16, the SIMD type digital signal processing unit 18, and the data output register (DOR) 20. The SIMD type digital signal processing unit 18 comprises a parallel arranged (connected) number of processing elements (PE0 to PEN−1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) 14, because the SVP core 12 operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on the circuit board. The mounting plate of the heat sink is provided with a plurality of openings through which the solder of the solder pad flows during the solder reflow process so that the mounting plate is securely adhered between the power transistor and the circuit board. The mounting plate of the heat sink is connected thermally to an extension member which extends generally perpendicular to the mounting plate, the extension member in turn being connected to a heat dissipation surface which may be one or several fins.

Abstract: Memory devices and methods are presented for selectively reading or writing rows or columns of memory cells in a ferroelectric memory array, wherein sense amps are selectively coupled with row lines or column lines and decoder outputs are coupled with column lines or row lines for row or column memory access operations, respectively.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Abstract: The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus device if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus. Address and data FIFO buffers are used for writes to a second bus device.

Abstract: The present invention overcomes the disadvantages of the prior art and provides a new temperature compensation trimming technique. Temperature compensated output is provided in a logarithmic voltage output device by the steps of: measuring the resistance of a first resistor, a second resistor, and a third resistor at a first temperature; measuring again the resistances of the first resistor, second resistor, and third resistor at a second temperature; and trimming the drift of the third resistor according to a calculated temperature compensation trim.

Abstract: A detector (55) and method for detecting a synchronization servo mark (SSM) in a data stream of mass data storage device (10) has a matched filter (56) to receive the data stream. The filter (56) produces a maximum output when the SSM is applied. A delay element receives (64) the matched filter output to produce a delay element output (72). When the delay element output (72) is greater than a predetermined threshold value (Vth) and is larger than the output value (74), the (SSM) is in a current time location. When the “D” element output (72) is greater than the predetermined threshold value (Vth) and less than the output value, the SSM is in the next time location. The threshold may be established to be less than maximum if the phase of the SSM is within a predetermined phase range.

Abstract: A movable mirror device driven by a reluctance force motor is provided. A sheet of material has a mirror portion, a hinge portion, and a frame portion formed therein. The mirror portion is coupled to the frame portion via the hinge portion. The reluctance force motor is formed from a magnetic flux channeling circuit. A wire coiled about a portion of the magnetic circuit is used to induce a magnetic field through the magnetic circuit. Air gaps in the magnetic circuit provide attractive forces between portions of the magnetic circuit when a magnetic field is present in the magnetic circuit. The air gaps and the magnetic circuit are configured so that the magnetic attractive forces at the air gaps exert torque on the mirror portion about the hinge portion. When the hinge portion is twisted, it acts as a torsional spring biasing the mirror portion toward a neutral relaxed position.

Abstract: A type of semiconductor device and its manufacturing method, which can further miniaturize semiconductor devices and reduce design restrictions by minimizing the fillet around the semiconductor chip. The semiconductor package is constituted by fixing semiconductor chip 100 on insulating substrate 102 via die paste 104. Semiconductor chip 100 has top surface 112, where an electronic circuit is formed, and a bottom surface 114 adhered to insulating substrate 102. The bottom surface 114 is formed smaller than top surface 112. By forming bottom surface 114 smaller than top surface 112, the amount of the fillet spread out around semiconductor chip 100 can be reduced.

Abstract: An implementation of a multi-dimensional Galois field multiplier and a method of Galois field multi-dimensional multiplication which are able to support many communication standards having various symbol sizes, different GFs, and different primitive polynomials, in a cost-efficient manner is disclosed. The key to allow a single implementation to perform for all different GF sizes is to align the input data such that the Galois field symbols of the operands are aligned to the left most significant bit (MSB) position of the input data field. Similarly, the primitive polynomial used to create a selected Galois field is aligned to the left MSB position. A polynomial multiply is performed. The product polynomial is then conditionally divided by the primitive polynomial starting with the most significant bit, the condition being if the left most bit of the product is a 1. In other words, if the product polynomial has an MSB of 1, then divide the product with the primitive polynomial.

Abstract: A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) and contains a shared memory (44) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller (134) receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller (134) and ATM transmit controller (132) operate in a simple streaming mode. A host interface controller (135) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.

Abstract: A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region.