Abstract: A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and activity time within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor. Yet other embodiments disclose, depending upon the respective embodiment, a processor, comprising a monitor for measuring the relative amount of idle time, activity time or idle time and activity time within the processor, results of the measuring being used by the processor to control power dissipation associated with the processor.

Abstract: An optical matrix switch station (1) is shown mounting a plurality of optical switch units (15, 17), each of which includes a mirror (29), moveable in two axes, for purpose of switching optical beams from one optical fiber to another. A mirror assembly (41) includes a single body of silicon comprising a frame portion (43), gimbals (45), mirror portion (47), and related hinges (55). Magnets (53, 54) and air coils (89) are utilized to position the central mirror surface (29) to a selected orientation. The moveable mirror and associated magnets along with control LED's (71) are hermetically packaged in a header (81) and mounted with the air coils on mounting bracket (85) to form a micromirror assembly package (99) mounted in each optical switch unit.

Abstract: Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer uniformity, high throughput and at a relatively low deposition temperature. In one aspect, a source reagent solution comprising a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium is provided. The source reagent solution is vaporized to form a precursor vapor. The precursor vapor is introduced into a chemical vapor deposition chamber containing the substrate. In another aspect, before deposition, the substrate is preheated during a preheating period. After the preheating period, the substrate is disposed on a heated susceptor during a heating period, after which a PZT film is formed on the heated substrate.

Abstract: The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary scan paths and three additional test bond pads. This structure provides for testing these circuits without the need physically to contact the functional bond pads. For an output buffer, one switch opens the connection between the output of the functional circuits and the input of the output buffer. A second switch connects the first test bond pad to the input of the output buffer. A third switch connects the second test bond pad to the output of the output buffer. A fourth switch connects the third test bond pad to the output of the output buffer. For an input buffer, separate first and second switches respectively connect the second and third test bond pads to the input of the input buffer. A third switch connects the first test bond pad to the output of the input buffer.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.

Abstract: A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential mode bandwidth while maintaining common-mode and differential mode stability. An exemplary differential input, differential output (DIDO) amplifier comprises a pair of op amps having a compensation capacitance circuit. The compensation capacitance circuit is configured to distinguish between differential mode signals and common mode signals, and to reduce the effects of compensation capacitance during differential mode operation, but allow the effects of compensation capacitance to remain present during common mode operation. As a result, the amount of compensation capacitance can be configured such that common mode stability can be maintained without reducing differential mode bandwidth. The DIDO amplifier can be configured as a programmable gain amplifier or a fixed gain amplifier.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer through orifices (110) contained in the spokes (90).

Abstract: A test apparatus (300) comprising a single handler (304) is coupled to a first tester (336) and second tester (308). A first test procedure is performed on a set of second IC's using the first tester (336), simultaneously while a second test procedure is performed on a first set of IC's using the second tester (308). Sets of IC's are tested sequentially, in parallel, by a plurality of testers (336/308) within a single handler (304).

Abstract: A system is provided for wavelet-based compression of an audio sample set including multiple audio samples. For each of the audio samples, the system receives the audio sample and, according to a psychoacoustic model, determines perceptually important information in the audio sample. The system decomposes the audio sample into multiple sub-bands according to a Wavelet Packet Transform and allocates bits to each of the sub-bands of the audio sample according to the determined perceptually important information in the audio sample. The system compresses the audio sample according to the allocation of bits to the sub-bands. The plurality of compressed audio samples includes a compressed audio sample set usable to generate a plurality of synthesized audio signals.

Abstract: The present invention provides a method for manufacturing a semiconductor device, an associated method for manufacturing an integrated circuit, and an LDMOS device manufactured in accordance with the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, may include depositing a layer of photoresist material over a substrate and creating an active device opening having sidewall angles associated therewith through the photoresist material. Additionally, the method may include forming a dummy opening through the photoresist material, wherein the dummy opening is located proximate the active device opening to reduce a shrinkage of the photoresist between the dummy opening and the active device opening and thereby inhibit nonuniform distortion of the sidewall angles.

Abstract: A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).

Abstract: An integrated circuit resistor (150) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (74) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (150) during the formation of metal silicide regions (140) on the integrated circuit resistor (150).

Abstract: A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr;k(i)=(zk−yk(i))2−&agr;(i), wherein &agr;(i) is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr;k(i) is a branch metric at time k for an ith Viterbi branch, k is a time period, zk is a received value at time k, &lgr;k(i) is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an ith branch, ak, ak−1, ak−2, ak−3 are received state values at respective time periods k, k−1, k−2, and k−3, and yk is an ideal sample associated with an ith branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first (90) and second (92) possible decode values.

Abstract: An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current path resistor (160,158), and a biasing circuit (162,164) in series. Each side of the MR head 42 is connected between a respective one of the current path resistors (158,160) and the biasing circuits (162,168). A shunt resistor (170) is connected between the control transistors (154,156) and the current path resistors (158,160) in each of the current paths. When the control transistors (154,156) are not conducting, the current path resistors (158,160) and the shunt resistor (170) shunt the MR head (42).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).