Patents Assigned to Texas Instruments
  • Patent number: 6728950
    Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
  • Patent number: 6727752
    Abstract: A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David L. Skinner, Wayne Tien-Feng Chen, David A. Grant, Vadim Ivanov
  • Patent number: 6728302
    Abstract: A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output signal corresponding to a magnitude of the input signal. A control circuit (726) is coupled to receive the output signal, a first reference signal (&eegr;1) and a second reference signal (&eegr;2). The control circuit is arranged to produce a control signal in response to a comparison of the output signal, the first reference signal and the second reference signal.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Ganesh Dabak, Timothy M. Schmidl, Srinath Hosur
  • Patent number: 6727722
    Abstract: Integrated circuit die on a wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the wafer. The process connects first and second bond pads of a first die to provide a test path through the first die. The process applies a test signal to a second die connected to the second bond pad of the first die. The process passes the test signal from the first bond pad of the first die along the test path through the first die to the second bond pad of the first die and then to the second die.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 6728320
    Abstract: A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first capacitor and a second capacitor in parallel, linking a first circuit to a second circuit. First digital data is transferred from the first circuit to the second circuit, and a reference clock is provided by the first circuit and transmitted with the first data to the second circuit for recovery thereby. A first set of bi-level signals representing the zero values of the first data is applied to the first capacitor, such that a repeating level transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing the one values of the first data is applied to the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The clock and data are then recovered.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Himamshu G. Khasnis, Anjana Ghosh, Krishnan Ramabhadran, Manoj S. Soman, Srinivasan Venkataraman
  • Patent number: 6727755
    Abstract: A two stage amplifier circuit (10), the first stage (12) comprising a modified quad configuration and the second stage (14) comprising a translinear current amplifier configuration. The present invention achieves the advantages of fast response time, low distortion and improved bandwidth. The current gain of the second stage is represented by: (IAout1−IAout2)/(Iout1−Iout2)=(1+R123/R124)·(I135/I134)·(A/(1+A)) where A=gmQ109·R124.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Muhammad Islam, Herman Theodorus, Kambiz Hayat-Dawoodi
  • Patent number: 6727757
    Abstract: A transconductor circuit, including a differential transconductor amplifier circuit. The transconductor circuit includes an input pair of transistors adapted to receive a differential input voltage, as well as a pair of output terminals adapted to provide a differential output current. A second pair of transistors provides current to the input pair of transistors. A floating voltage circuit is adapted to generate a floating voltage corresponding to a common-mode voltage of the differential output nodes and to control the second pair of transistors in response to the floating voltage to stabilize the common-mode voltage of the differential transconductor amplifier circuit.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incoporated
    Inventors: Srinivasan Venkatraman, Abhijit Kumar Das
  • Patent number: 6727131
    Abstract: A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiqiang Wu, Kaiping Liu
  • Patent number: 6727578
    Abstract: A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped substrate (302) and an epitaxial layer (304) formed over the substrate (302). In one embodiment (200), a surrounding conductive structure (202) is formed on the peripheral edges of the semiconductor device (200) die. The surrounding conductive structure (202) is coupled to the substrate (302). In another embodiment, the back side of the die (404) is coupled to the conductive portion (402) of an integrated circuit package. The conductive portion (402) is coupled to a power supply voltage. In another embodiment (700), the surrounding conductive structure (702) is coupled to a power supply voltage by one or more bond pads (710) formed on, or coupled to, the surrounding conductive structure (702).
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David B. Scott, Heng-Chih Lin
  • Patent number: 6728838
    Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block circuitry (700, 702) is connected to the set of valid bits and dirty bits and is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register (700) and an end register (702) each separately loadable by the processor. The block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not. Likewise, the block circuitry can clean a single line or a block of lines in response to an operation command from the processor.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre
  • Patent number: 6728915
    Abstract: This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated for test and not used functionally. The control scan cells can be scanned while the circuit is in functional mode, since their memories are dedicated. However, the data scan cells can only be scanned after the circuit transitions into test mode, since their memories are shared. This boundary scan system advantageously provides; (1) lower test circuitry overhead since the data scan cells use shared memories, (2) safe entry into test mode since the control scan cells can be scanned during functional mode to pre-load safe control conditions, and (3) avoidance of floating (i.e. 3-state) busses that can cause high current situations.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 6728301
    Abstract: A method is providing for calculating local oscillator phase errors in a code division multiple access (CDMA) receiver using an arctangent calculation of the difference vectors between sample stream (multipath) delays. Instead of the conventional cross-product calculation of pilot symbols, a phase correction, using both real and imaginary parts of the complex conjugate, is preformed in each sample stream delay path before the step of maximal-ratio combining (MRC). The weighted combination is then selectively filtered and accumulated, depending on whether the automatic frequency control (AFC) loop is tracking or acquiring. Then, an arctangent polynomial approximation is used to find the actual phase error. An AFC system using the above-mentioned MRC combination and arctangent calculation of phase error is also provided.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: April 27, 2004
    Assignees: Texas Instruments Incorporated, Koninklijke Philips Electronics N.V.
    Inventor: George Chrisikos
  • Patent number: 6728741
    Abstract: A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises a first input operand (182) consisting of a first half of an N×N bit data block and a second input operand (184) consisting of a second half of an N×N bit data block. A first hardware bit transformation (188) forms an upper half of an N-way bit deal of the two operands (186), and a second hardware bit transformation (192) forms a lower half of the N-way bit deal (190). The upper and lower halves of the N-way bit deal represent a diagonally mirrored image (172) of the N×N bit data block. The method retrieves a data block from memory and packs it into two input operand registers. The two hardware bit transformations fill respective destination registers. The data is unpacked from the destination registers and stored to memory.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: John Keay
  • Patent number: 6728128
    Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: April 27, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Akitoshi Nishimura, Yukio Fukuda, Katsuhiro Aoki
  • Publication number: 20040078557
    Abstract: Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Maija Kuusela, Serge Lasserre
  • Publication number: 20040078528
    Abstract: A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor's coherence buffer, and information associated with the first processor's write transaction is stored in the second processor's coherence buffer to maintain data coherency between the first and second processors.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre, Maija Kuusela, Dominique D'Inverno
  • Publication number: 20040075479
    Abstract: A master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received. Due to such receiving, the number of transistors/area and/or power consumption requirements (efficiently) may be minimized in implementing a flip-flop. The feedback path may be implemented using a single pass-gate, further enhancing the efficiency of implementation. In addition, clock enable/disable signals may be generated efficiently taking into account an externally received flip-flop disable signal and absence of transitions in the data input bits. When the flip-flop is implemented to support ATPG type sequential scanning testing, a multiplexor may be implemented efficiently to select either the data bits or scan bits.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Sushil Kumar Gupta
  • Publication number: 20040078531
    Abstract: A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's core. The local data stack is coupled to the main stack and is located internal to the processor's core. The local data stack has a plurality of entries that correspond to entries in the main stack. Each flag is associated with a corresponding entry in the local data stack and indicates whether the data in the corresponding local data stack entry is valid. The system performs two instructions. One instruction synchronizes the main stack to the local data stack and invalidates the local data stack, while the other instruction synchronizes the main stack without invalidating the local data stack.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre
  • Publication number: 20040078550
    Abstract: A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre, Maija Kuusela, Dominique D'Inverno
  • Publication number: 20040078523
    Abstract: A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 22, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Maija Kuusela, Dominique D'Inverno