Abstract: A low drop out linear voltage regulator (200) overcomes the dynamic quiescent current limitation by creating an internal zero that moves in the same direction and has the same amplitude as that of the output pole without sensing a portion of the load current. The low drop out linear voltage regulator (200) having frequency compensation in accordance with the present invention includes an error amplifier (202), a NMOS pass transistor (204), a variable compensation network (Ci, 206), and a stabilization circuit (208, 210, I3, I4). The error amplifier (202) includes a power supply input connected to a first power supply, a non-inverting input coupled to a reference voltage, a inverting input and an output terminal. The NMOS pass transistor (204) includes a source connected to an output terminal of the voltage regulator, a drain coupled to the second power supply, and a gate coupled to the output terminal of the error amplifier. The variable compensation network (Ci, 206) connects to the error amplifier.

Abstract: An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is controlled by a controller. The rotation of the workpiece within a solution containing conductive material is controlled by a rotation controller. The current level and/or rotation of the workpiece is controlled in such a way that the non-uniform growth of large grains within the conductive film is minimized.

Abstract: A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A first bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a predetermined size, is arranged to conduct a collector current from the first mirror transistor. A second bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a size that is proportional to the size of the emitter area of the first bipolar transistor, is arranged to conduct a collector current from the second mirror transistor, the base thereof being connected to the collector thereof.

Abstract: The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like contours after the reflow process—a result achieved by using the solder material in tapered openings of a thick sheet-like elastic polymer adhered to the BGA substrate and selected for its characteristics of non-wettability to solder and volumetric shrinkage greater than solder.

Abstract: A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

Abstract: A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Abstract: The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in peripheral storage device systems. The system provides for more efficient media storage/retrieval and addresses the issue of channel latencies in media storage/retrieval systems.

Abstract: A modeling technique for selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a conventional foot print of a ball grid array (BGA) package, or land grid array package (LGA) to improve device reliability. The modeling technique anticipates a routing of traces through the gap resulting from the depopulated solder balls or lands as additional space for routing traces or lines from solder ball or land pads to an exterior surface of a substrate (14) upon which a semiconductor die (20) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls or lands on ever shrinking packages, thereby increasing device reliability.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle.

Abstract: A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.

Abstract: A security system to enable authenticated access of an individual to a protected area, including a remote control unit (22) with a transponder (28), carried by the individual, which transmits an identification code group on reception of an interrogation signal. A control unit located within the protected area transmits an interrogation signal when activated by the individual, and verifies the identification code group received from the transponder. Access to the protected area will only be permitted on positive verification of the right to access. The transponder (28), contained within the remote control unit (22), is a passive transponder which obtains a supply voltage from the interrogation signal transmitted by the control unit (16) and then feeds this to a supply voltage rail.

Abstract: A method for controlling an optical, path-to-sight link, the optical link including a source of light having a beam of light, a controllable beam steering device and an actuator to permit steering the light beam, the beam steering device being controllable by predetermined control signals. The method includes the following steps. The beam steering device is controlled so as to scan the beam of light in a first predetermined pattern. First direction is received data from a remote receiver including a light detector, the direction data corresponding to a direction of the beam at which the scanned beam of light is detected by the light detector. Responsive to the first direction data, a first beam direction is determined for data communication from the link to the receiver. The beam steering device is controlled to maintain a communications beam direction corresponding to the first beam direction. The beam of light is modulated with electronic signals.

Abstract: A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback driver circuits minimize (prevent) an amount of time both the NMOS and PMOS transistors are in an ON state at the same time, thereby reducing short circuit power (i.e., the power dissipated if both the PMOS and NMOS transistors are in an on state). In addition, as the two feedback driver circuits do not contain common input inverter circuits, the short circuit power is further reduced.

Abstract: A processor may comprise fetch logic that retrieves instructions from memory, decode logic coupled to the fetch logic, and an active program counter selectable as either a first program counter or a second program counter. Further, an instruction may be replaced by a micro-sequence comprising one or more instructions and the active program counter also may switch between the first and second program counters.

Abstract: Methods and apparatuses are disclosed for managing a memory. In some embodiments, the apparatuses may include a processor, a memory coupled to the processor, a stack that exists in memory and contains stack data, and a memory controller coupled to the memory. The memory may further include multiple levels. The processor may issue data requests and the memory controller may adjust memory management policies between the various levels of memory based on whether the data requests refer to stack data. In this manner, data may be written to a first level of memory without allocating data from a second level of memory. Thus, memory access time may be reduced and overall power consumption may be reduced.

Abstract: A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines the mode of operation for the decode logic for subsequent instructions. In particular, the decode logic operating in a current mode concurrently with the pre-decoder detecting a predetermined prefix, which indicates a subsequent instruction is a system command. Upon detecting this predetermined prefix, the decoder decodes the system command accordingly.

Abstract: Correcting a mask pattern includes accessing a record associated with an uncorrected pattern that comprises segments. The record associates each segment with a correction grid of a number of correction grids, where each correction grid comprises points. A segment is selected, and an optimal correction for the segment is determined. A correction grid associated with the segment is determined. The segment is snapped to a subset of points of the associated correction grid, where the subset of points is proximate to the optimal correction, to form a corrected pattern of a mask pattern.

Abstract: A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).

Abstract: A first processor executes a transaction targeting a pre-determined address, wherein the transaction is detected by a wait unit that asserts a wait signal to cause the first processor to enter a wait mode. The wait signal is de-asserted when the wait unit receives a signal from another processor or when a system interrupt occurs.