Abstract: A laser alignment structure and method for fabrication such a structure is provided. Preferably, the same material is used throughout the alignment structure. Contrast between different areas of the alignment structure is achieved by providing areas in the structure which are relatively flat and other areas which are not relatively flat having varying topographical features. The relatively flat areas reflect impinging laser energy substantially back in the direction from which it came (e.g., in a direction substantially perpendicular to a plane defined by the surface of the structure). The relatively non-flat areas reflect relatively little, if any, laser energy in the direction from which it came. Thus, although the entire surface of the alignment structure may be reflective of laser energy, the surface topology changes from one area to another thereby effectively changing the direction of the reflected laser energy.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

Abstract: A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the liner (14) to both unlock and lower the heated liner, such as a silicon carbide liner, at an controlled rate. The fixture is also adapted to elevate a new liner into the operating vertical furnace at a controlled rate to control the rate of heating of the liner as it is inserted into the operating vertical furnace. The fixture includes an inner ring (34), a low-friction Teflon® ring (36), and an outer ring (38) permitting the rotation of the inner ring within the outer ring. Advantageously, the low friction ring comprises a flanged portion and a vertical portion allowing rotation of the inner ring within the outer ring even when elevated at extreme temperatures exceeding 500° C.

Abstract: A talking book and a method of authoring a talking book is presented where the talking book includes a synthesizer, an audio system, a memory, a display, and switches for selecting pages and/or chapters of the talking book. The talking book is authored by a script that lists speech files, the sampling rate, and the chapter and page boundaries. Configuration tables and segment tables are generated from the script and these tables are assembled with a playback program to combined binary data stored in the talking book.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Abstract: Resistance to corrosion of aluminum metallization on semiconductor devices during wafer sawing process is provided by a sacrificial anode containing magnesium in contact with the integrated circuit wafer and the dicing saw. A relatively thin film or disc of magnesium directly in contact with the surface of the dicing blade makes use of cooling water to serve as the electrolyte between the magnesium and aluminum surfaces, and in turn corrosion is transferred to the magnesium anode in preference to the aluminum of the semiconductor device.

Abstract: A system and method are disclosed to help protect a node of associated circuitry from overshooting or undershooting, such as can be associated with power up or other transitional modes. The protection is implemented by diode connecting a transistor, which has its base electrically coupled to the node during the transitional mode. Either after a predetermined time period or after the voltage at the node has reached a desired level, the diode connection can be removed to permit normal operation to begin in which a bias can be provided to the node.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one scan path at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.

Abstract: Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

Abstract: A versatile flow cell front-end (104) for storing and delivering reagents, test samples, and other transportable materials within an optically-based integrated sensor device (100), where management of those materials is controlled via electrical connections (110, 114) within the optically-based integrated sensor device is disclosed, including an inlet chamber (118) formed within the flow cell, a sensing chamber (116) formed within the flow cell, an electrical interface (114) formed within the flow cell, a conduit (122) adjoining the inlet and sensing chambers, another conduit (124) adapted to dispose of fluid in the sensing chamber, and a fluidic control member (126) instantiated along the conduit and responsively coupled to the electrical interface.

Abstract: This invention cures many inefficiencies with known scan conversion methods. This invention employs an edge array rather than a set linked list from an array of pointers equal in number to the number of scan lines. This invention thus eliminates storage of linked list pointers which in the prior art included many null pointers resulting in better memory utilization. This invention sorts the active edge table only at edge intersections and vertices, thus eliminating much unneeded sorting. This invention permits integrated clipping of a subject polygon by a clip polygon and forming trapezoids filling the clipped area by activating trapezoid formation at every vertex of either polygon and at every edge intersection. This process saves code space and computer processing time. This invention efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors.

Abstract: An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for greater correction when error is large, and little correction when the error is small. The exponential curve may be viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Power consumption is optimized by implementing the offset generation circuit using capacitor charge sharing principles.

Abstract: The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).

Abstract: A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. During a design phase of an application, a set of algorithm modules is linked with a calling program to form an initial software program. Each of the set of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The calling program sends a query to the memory interface of each algorithm module to request memory usage requirements for each instance of the algorithm module. A response is then sent from the memory interface of each algorithm module identifying memory usage requirements for each instance of the algorithm module.

Abstract: A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion tools. The technique uses sigma-delta modulation technology to allow conversion of analog and mixed signal stimuli into digital representations that can be converted for use in the target tester using existing digital pattern conversion tools.

Abstract: An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive sub-circuit 302, each sub-circuit including an MOS transistor. The circuit comprises a direct connection between the I/O pad 303 and the drain 321 of the drive sub-circuit MOS transistor 306, and further a forward diode 360 inserted between the I/O pad 303 and the drain 311 of the discharge sub-circuit MOS transistor 305 to isolate the junction capacitance of the discharge sub-circuit MOS transistor, whereby electrical noise coupling to the substrate is reduced, RF/analog input signals are improved, and leakage at the I/O pad is reduced.

Abstract: A conveyor system (30) comprises: a boat (20), a feed belt (36), a feed pulley (38), and improved railings (34). The boat (20) is adapted to carry a component or components, such as semiconductor chips (32), therein. The feed belt (36) is driven by the feed pulley (38). The feed belt (36) is adapted to move the boat (20) along the conveyor system (30). The improved railings (34) are adapted to retain the boat (20) and to define a path for the boat (20). A set of bearings (44) are coupled to each of the improved railings (34) in locations such that the boat (20) will contact the bearings (44) rather than the railings (34) for at least part of the path as the boat (20) moves along the conveyor system (30).