Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Abstract: A circuit (30, 40) and method for detecting faults of a write head (18) of a hard-disk drive system (70). A first resistor R1 and a second resistor R2 are coupled to coil L of write head (18). A transistor Q1 is coupled to a common node of resistor R1 and R2. Current I0 is applied to the coil L, and voltages Vab and Vac across the nodes at either end of resistors R1 and R1 are analyzed in order to detect faults on write head coil L. The detection is performed during a quiet mode of the hard-disk drive system (70), so the fault detection is frequency-independent. Open faults are distinguishable from short-to-ground faults by the write fault detection circuit (30, 40).

Abstract: A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.

Abstract: Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in the top of the wafer between individual die areas. Material is then removed from the bottom side of the wafer in order to separate the individual dies. Methods are also disclosed for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for removing material from the bottom side of a wafer, and for securing a semiconductor device to a surface. Semiconductor wafers and dies are also disclosed having contoured bottom surfaces.

Abstract: The serial peripheral interface and high performance buffering scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, an improved high performance buffering scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. In accordance with an exemplary embodiment, a SPI comprises a single buffer having a high data rate, for example, at least the throughput of double buffer schemes, but without the increased size in logic area. To facilitate the throughput of data, the SPI single buffer can be configured with a queuing arrangement. The queuing arrangement for the SPI single buffer can comprise any queuing configuration, such as, for example, a circular queuing arrangement or a linear queuing arrangement.

Abstract: A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective information transfer between a peripheral storage device, such as a disk drive, a CDROM drive, or a tape drive, and a host computer in a serial or parallel data format. A cable connector and cable assembly are disclosed for connecting the peripheral storage device system with the host computer, whereby serial data transfer may be accomplished via an ATA connector on one or both of the peripheral storage device and the host computer. In addition, a methodology is disclosed for transferring data between a peripheral storage device and a host computer in one of a serial and a parallel data format.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).

Abstract: A method (30) of fabricating a micromechanical device (10) by performing spacer layer undercutting (46) and passivation at the package level. A back-end assembly process utilizes a full-cut saw process to separate the partially fabricated micromechanical devices. The individual die are then attached by pick and place equipment to a lead frame and are wire bonded, before the die are undercut. This technique avoids the generation of any particles from becoming lodged under movable structure during the cut process, and further, reduces the susceptibility of the die to damage or particles generated during the pick and place process.

Abstract: A method and apparatus of connecting an active computing device (15) to an active peripheral option (20) comprising the steps of making a physical connection (210) between the device (15) and the option (20) wherein the option (20) is communicably linked (44) to one or more peripheral devices (35, 40). A system interrupt signal is generated (240) and detected (250) by the system processor (17) causing all activity along the connection path between the device (15) and the option (20) to be suspended (250).

Abstract: A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback driver circuits minimize (prevent) an amount of time both the NMOS and PMOS transistors are in an ON state at the same time, thereby reducing short circuit power (i.e., the power dissipated if both the PMOS and NMOS transistors are in an on state). In addition, as the two feedback driver circuits do not contain common input inverter circuits, the short circuit power is further reduced.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A bus interface device includes a parallel input configured to be coupled to a bus (20), such as a primary PCI bus. The device also includes a parallel data output (TXD) and at least two control output nodes (TX_ER and TX_EN). Data control circuitry coupled to the control output nodes utilizes a coding scheme (e.g., an 8B/10B scheme) to generate one of a set of control codes (e.g., Idle, Extend, Normal Data and Error) to be provided to the control output nodes. The device also includes reset control circuitry that generates a specified sequence of control codes (e.g., a sequence of Idle's and Extend's) on the control outputs. This sequence can be used to communicate information such as a signal (e.g., reset signal) and/or a mode (e.g., a CRC mode).

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.

Abstract: Semiconductor wafers exhibiting increased mechanical strength and reduced susceptibility to fracture and methods of making the same are disclosed. The improved mechanical strength arises from a thin coating of a refractory material deposited on the backside of the wafer. Preferably, the coating is comprised of a ceramic. More preferably, the coating is comprised of silicon carbide. Also disclosed are methods for evaluating different coating materials.

Abstract: A method for processing data is provided that includes storing a write operation in a store buffer that indicates a first data element is to be written to a memory array element. The write operation includes a first address associated with a location in the memory array element to where the first data element is to be written. A read operation may be received at the store buffer, indicating that a second data element is to be read from the memory array element. The read operation includes a second address associated with a location in the memory array element from where the second data element is to be read. A hashing operation may be executed on the first and second addresses such that first and second hashed addresses are respectively produced. The hashed addresses are compared. If they match, the first data element is written to the memory array element before the read operation is executed.

Abstract: A method for processing an audio signal is provided that includes receiving an audio signal and integrating the audio signal with a selected one of a plurality of sound effects. The method also includes generating an output that reflects the integration of the audio signal and the selected sound effect. The output may then be communicated to a next destination.

Abstract: EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal amount of current, but in opposite direction, is caused to be flown in another pin (“third pin”) located close to the load pin. As a result, the EMI caused by the third pin cancels the EMI generated by the load pin. During a discharge phase, a fourth pin carries and equal amount of current, but in opposite direction, to that in the load pin. The third and fourth pins may be formed by power supply pin and ground pin. A control path may avoid a path from the third pin to the fourth pin during both the charging and discharging phases. In addition, the high load may be driven by a programmable driver which uses an amount of current proportionate to the extent of load, thereby avoiding parasitic currents. EMI is further reduced as a result.

Abstract: The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the semiconductor substrate with a channel region therebetween. The source and drain region of the semiconductor substrate are then subjected to an angled amorphization implant, wherein the angled amorphization implant amorphizes the semiconductor substrate thereat and in portions of the channel region near a lateral edge of the gate, thereby defining an amorphized source extension region and drain extension region, respectively. The method continue with an implantation of the source region and the drain region with a lightly doped p-type source/drain implant, followed by an anneal to repair damage in the semiconductor substrate due to the pre-amorphizing implant and the lightly doped source/drain implantation.

Abstract: A method of manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second surface (103a), in which the first surface (103b) or the second surface (103a) include a conductor pattern (104). The method also includes the step of disposing a plurality of conductive bumps (107) on the first surface (103b) of the substrate (103) and attaching a semiconductor die (102) to the second surface (103a) of the substrate (103). The method further includes the step of electrically connecting the conductive bumps (107) to the conductor pattern (104), such that electrically connecting the conductive bumps (107) to the conductor pattern (104) mechanically affixes the conductive bumps (107) to the first surface (103b) of the substrate (103).