Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Abstract: Methods and apparatuses are disclosed for managing a memory. In some embodiments, the methods may include issuing a data request to remove data from memory, determining whether the data is being removed from a cache line in a cache memory, determining whether the data being removed is stack data, and varying the memory management policies if stack data is being removed that corresponds to a predetermined word in the cache line. If the predetermined word in the cache line is the first word, then the cache line may be invalidated regardless of its dirty state and queued for replacement. In this manner, invalidated cache lines may be replaced by incoming data instead of transferring them to the main memory unnecessarily and removing other more valuable data from the cache. Thus, number of memory accesses may be reduced and overall power consumption may be reduced.

Abstract: A system comprising a counter adapted to monitor the memory consumption of the allocated memory resources. Upon reaching or surpassing the memory resource threshold provided, the counter may indicate the need for garbage collection. The garbage collector assesses the memory and releases memory resources that are consumed by the programs but are not needed anymore. The recycled memory resources are thus provided to the programs and the counter is updated accordingly. In addition, the system may also include instructions requesting memory resources. After detecting such instructions, the memory usage counter is updated either by the exact amount of memory allocated or the. estimated amount of memory allocated. The counter may be implemented in hardware or in software.

Abstract: A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.

Abstract: A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in the instruction. Based on the outcome of test, the subsequent instruction is executed or skipped. Further, the instruction includes at least one bit that specifies how the test is to be performed. The bit may specify that the immediate value is to be compared to the register value, or that the immediate value is used to mask the register value and the masked register value has one or more of its bits tested.

Abstract: A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the particular computing platform (10). The manufacturer certificate may also store configuration parameters and device identification numbers. A secure run-time platform data checker (200) and a secure run-time checker (202) check the system firmware during operation of the computing platform (10) to ensure that the system firmware (30) or information in the manufacturer certificate (36) has not been altered. Application software files (32) and data files (34) are bound to the particular computing device (10) by a platform certificate (38). A key generator may be used to generate a random key and an encrypted key may be generated by encrypting the random key using a secret identification number associated with the particular computing platform (10). Only the encrypted key is stored in the platform certificate (36).

Abstract: Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.

Abstract: A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines if subsequent instructions switches the decoder from one mode to the other temporarily or permanently. In particular, the pre-decoder examines at least five Bytecodes concurrently with the decoder decoding a current instruction from a particular instruction set. If the pre-decoder determines that at least one of the five Bytecodes includes a predetermined instruction, the predetermined instruction is skipped and a following instruction is loaded into the decode logic and the decode logic switches from one mode to the other for the decoding of at least the following instruction.

Abstract: A contact for a pin receiving socket includes, in order, a top flange, an angled pin guiding portion, a first contact point, a recess, a second contact point, a flex shaft, an anchor portion, and an external connection portion. The contact, and preferably two identical contacts, is mounted in a pin receiving opening of a socket body. The anchor portion is secured in the socket body at the bottom of the pin receiving opening, and the external connection portion extends through and out of the socket body. When a pin is inserted, the first contact point rubs or wipes any debris or contaminants from the pin and the second contact point makes and electrical connection to the cleaned part of the pin.

Abstract: A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the execution of the two instructions may be parallelized if the two instructions are within a hardware loop. The processor thus, may implement a multiply and accumulate process in an efficient manner by performing the multiply instructions concurrently with the add instructions (which require fewer cycles to complete than the multiply instructions).

Abstract: A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of addressable matrices. A control circuit (700) is coupled to receive a delay value and a clock signal. The control circuit is arranged to address a selected matrix from the plurality of addressable matrices in response to the delay value and the clock signal. A backward register circuit (420) is coupled (712) to receive the selected matrix. The backward register circuit is arranged to produce a plurality of shifted matrices from the selected matrix in response to the clock signal. A logic circuit (330-354) is coupled to receive the state matrix, the selected matrix and the plurality of shifted matrices. The logic circuit produces a logical combination of the state matrix and each of the selected matrix and the plurality of shifted matrices.

Abstract: An application specific integrated circuit or ASIC (MSC) is connected to a plurality of bridge type sense elements (1-6) for analog multiplexing (10a, 10b, 10c) the outputs from a selected sense element to a common signal conditioning path (10f). The bridge type sense elements are biased through an electronically programmable resistor (10d1) to derive a temperature signal. The signal conditioning path provides electronically programmable correction for offset and gain proportional to the sensed condition, e.g., fluid pressure. Complete sensor characterization data provided at the time of manufacture is stored in non-volatile memory (10h) which is downloaded to a host controller (12) on command. The ASIC also includes diagnostic test bridges (BR1, BR2) for diagnosing ASIC faults and a signal diagnostic path (10m) for diagnosing sense element and sense element connection faults.

Abstract: The present invention discloses drive apparatus for rotating a mirror used for switching light signals. The drive apparatus has reduced internal wiring and uses a base printed circuit board which is mounted to a support printed circuit board by sandwiching conductive ball connections between matching traces or pads on the two printed circuit boards. A drive module is also included between the two printed circuit boards which can be either a drive coil or an electrostatic plate and is used to rotate the mirrors. The use of the bump grid array or conductive ball connections significantly reduces the amount of internal wiring required.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: The invention provides systems, methods, and devices that compensate for temperature, frequency, and sampling effects in a broadband communication device's power measurements. One embodiment of a system includes a thermal device, and an automatic gain control circuit coupled to the thermal device. One method includes the acts of disabling a TOP operation, setting a RF input power, reading an AGC GAIN value, and setting the broadband communications device based on the read AGC value. Furthermore, a broadband communications device according to the invention may operate by disabling a TOP operation, setting a RF input power, reading an AGC GAIN value, and setting the broadband communications device based on the read AGC value.

Abstract: A system (100) for generating image compression matrices is disclosed. The present invention includes an image (102) having pixel block arrays (104). The present invention also includes a transformer (106) that performs discrete cosine transforms on the pixel block arrays (104) to generate a discrete cosine transform array (107). The present invention also includes a quantizer (108) that receives the discrete cosine transform array (107) and retrieves a quantization coefficient matrix (110) and a model metric (112). Quantizer (108) partitions the quantization coefficient matrix (110) with the model metric (112) to generate a quantization matrix (115). Quantizer (108) also quantizes discrete cosine transform array (107) with the quantization matrix (115) to create a quantized array (117). The present invention also includes an encoder (120) that compresses the quantized array (117).

Abstract: A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller flex-frame (60) positioned within the support base (40). A wafer film transfer cylinder (30) encompasses a wafer breaking device (12), such as a convex dome. The transfer cylinder (30) is slidable downwardly with respect to the dome (12) to first stretch the wafer tape (51) and then transfer the wafer (56) from the larger frame (50) to the smaller frame (60) after dome (12) breaks the wafer (56) into die. The transfer cylinder (30) is heated to facilitate removing the saw tape (51) from the larger frame (50) after transfer to the smaller frame (60). The transfer cylinder (30) is juxtaposed with the smaller frame (60) residing within a cavity (48) of the support base (46). The present invention is suited for automated wafer transfer carriers which advance the broken wafer to pick and place equipment for packaging of the die.

Abstract: A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency of the semiconductor switch has a transmission gate coupled between the gate of the semiconductor switch and a second capacitor. The transmission gate is turned ON only when the gate of the semiconductor switch is about to make a positive or negative transition and isolated from the first and second voltage sources. A portion of the charge stored in the parasitic capacitance of the gate of the semiconductor switch can be stored in the second capacitor and reused to partially drive the semiconductor switch from the second to the first ON/OFF state. A further embodiment employs this technique with a synchronous rectifier in the regulator circuit.

Abstract: A method for forming a scaled static random access memory (SRAM) cell (10) based on an initial SRAM cell for implementation in a technology scaled from an initial technology. The SRAM cells comprise a plurality of transistors. The method comprises determining a reduction in a minimum gate length (46) for the scaled transistors (14, 16, 18) as compared to a minimum gate length for the initial transistors. The method also comprises forming a scaled drive transistor (16) comprising a gate having a gate length (54) reduced as compared to a gate length for an initial drive transistor. The scaled gate length (54) is reduced by less than the determined reduction in the minimum gate length (46).

Abstract: A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer filter of the receiver with the phase of the received signal.