Abstract: A power supply feedback circuit includes a regulating element at an input side of an optical isolator. The control lead for the regulating element is connected to a voltage divider to receive the divided voltage. A bypass circuit is provided on the voltage divider to change the resistance in a bypassed branch of the voltage divider during start up of the circuit. The bypass time depends on charging of a capacitor at a control lead, base or gate, of an active element by the bypass circuit. The output voltage of the circuit is brought gradually to the desired level as the capacitor charges and the active element removes the bypass from the voltage divider or applies the bypass to the voltage divider.

Abstract: A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register. The arbitration circuitry is operable to schedule access to the shared resource according to the access priority values provided by the processors. A software priority state is established during execution of an instruction module on each of the several processors. An instruction is executed on each processor to form an access request to the shared resource. An access priority value is provided with each access request that is responsive to the software priority state of the respective processor.

Abstract: A method and system of detecting whether the intensity of light incident a spatial light modulator varies periodically. One embodiment provides a method of operating a spatial light modulator, the method comprising: determining a peak level of light incident the modulator over a period of time; setting a threshold level equal to a fraction of the peak level; monitoring a current level of light incident the modulator; comparing the current level of light and the threshold level; and disabling the modulator based on the comparison. Another embodiment provides a modulator array.

Abstract: A system and method for providing a controllable virtual environment includes a computer (11) with processor and a display coupled to the processor to display 2-D or 3-D virtual environment objects. Speech grammars are stored as attributes of the virtual environment objects. Voice commands are recognized by a speech recognizer (19) and microphone (20) coupled to the processor whereby the voice commands are used to manipulate the virtual environment objects on the display. The system is further made role-dependent whereby the display of virtual environment objects and grammar is dependent on the role of the user.

Abstract: The present invention provides a method, system and apparatus of interfacing a CardBay device (520) using existing Card and Socket Services (CSS) software (530). A CardBay controller (515) responds to card queries to indicate a pseudo card configuration which the CSS software (530) will recognize and support without the need for modification. The CardBay controller (515) further overrides the power control request generated in response to the pseudo card configuration information and signals a power control based on the voltage combination associated with the actual CardBay device (520). The controller also intercepts CIS read commands and responds with a CIS recognizable and specific to the inserted card. The controller (515) can further intercept legacy driver accesses and convert them into CardBay recognized accesses.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.

Abstract: A chamber (10) for applying material to the surface of a semiconductor wafer (18) located in the chamber by means of cathodic sputtering a target (26), located on a target mount (24), of the material to be applied or a component thereof, contains a wafer mount (14) on which the semiconductor wafer (18) to be coated is located. The wafer mount (14) is provided movable in the chamber (10) between a charging position for application of the semiconductor wafer and a sputtering position in which semiconductor wafer is located at a predefined distance away from and opposite to the target. Provided in the chamber is a shielding support (30) which is supported by the edge of the semiconductor wafer in the sputtering position in maintaining it in contact with the wafer mount, the shielding support extending between the edge of the semiconductor wafer and a portion adjoining the edge of the target on the target mount and thus defining a sputtering space between the target and the semiconductor wafer.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion is provided. According to one aspect, the window frame can be formed from a unitary piece of sheet metal. A transparent piece is attached to the inner portion of the window frame through a molding process. According to one embodiment, the window frame is placed within a mold such that the inner portion of the window frame projects into an inner cavity inside the mold. After the mold has been closed, a transparent material is injected into the inner cavity so that it bonds with the inner portion of the window frame. After the bond of between the transparent material and the window frame is set, the window frame/window piece assembly is removed from the mold. According to another embodiment, a plurality of window frames may be loaded into a single mold so that a plurality of window frame/window piece assemblies can be fabricated in a single batch.

Abstract: A method for creating electrical interconnects between a semiconductor die and package. In the preferred embodiment, an insulating material is applied over the die and extends to the substrate contact pads, leaving a portion of each contact pad exposed. Holes are then trimmed through the insulating material, exposing at least a portion of each die bond pad. A conductive material is then applied over the die, flowing into the holes, contacting the die bond pads, and extending out to contact at least a portion of each substrate contact pad. In another preferred embodiment, an electrically conductive bump may be formed on each die bond pad, protruding through said non-conductive material and at least partially through said conductive material. The conductive layer is then laser trimmed, forming conductive patches that serve as electrical interconnects between the die and package substrate.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data is loaded into various lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache, such as a task ID. A miss counter (532) counts each miss and a monitoring task (1311) determines a miss rate for memory requests. If a selected miss rate threshold value is exceeded, the digital system is reconfigured in order to reduce the miss rate.

Abstract: The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a plurality of patterned electrically conductive metal layers within a scribe line. The plurality of metal layers further comprises one or more lower metal layers comprising a plurality of split pads longitudinally spaced along the length of the scribe line, wherein a channel traversing the length of the scribe line is define. One or more top metal layers comprising a plurality of solid pads generally residing over the split pads defines a plurality of columns of pads. One or more conduits generally residing within the channel are associated with one or more lower metal layers and connect two or more split pads associated with the respective one or more lower metal layers, wherein a bow-tie lead is defined.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions.

Abstract: A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a first-in-first-out fashion at the data source ports. Each data transfer request has a priority level for execution. In effective channel priority processing the priority level assigned to a source port is the greatest priority level of any data transfer request in the corresponding first-in-first-out queue. This techniques prevents a low priority data transfer request at the output of a source port queue from blocking a higher priority data transfer request further back in the queue. Raising the priority of all data transfer requests within a source port queue enables the low priority data transfer request to complete enabling the high priority data transfer request to be reached.

Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (ƒ), by way of a minimization of the frequency error.

Abstract: In one embodiment of the present invention, a contact structure of a semiconductor device within an integrated circuit includes an active region, the active region having been defined using a mask provided on a substrate. The contact structure further includes an isolation region adjacent the active region and including a field oxide: the field oxide having been grown by exposure of the substrate to a thermal process and an oxygen-containing gas; a film having been formed on a top surface of the mask during exposure to the thermal process and oxygen-containing gas; a dry etching process having been performed to substantially remove the film from the top surface of the mask and to remove a top portion of the field oxide in the isolation region; and a wet etching process having been performed to substantially remove any portion of the mask remaining after the dry etching process.