Abstract: An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to output a held signal, a buffer circuit to buffer the held signal to output a buffered signal, and a comparator circuit to compare the buffered signal with a reference voltage.

Abstract: A method for symbol detection using a decision feedback equalizer loop is provided comprising the steps of generating a delay-less symbol estimate from data redundancy in a received signal, and employing said delay-less symbol estimate in said decision feedback equalizer (DFE) loop as input to the feedback section of the DFE and/or to update equalizer parameters. A receiver for digital signals is also provided. Other systems, apparatus and methods are also disclosed.

Abstract: Detecting a defect of an integrated circuit includes illuminating an integrated circuit with an optical beam. The integrated circuit includes a substrate, a dielectric layer disposed outwardly from the substrate, and a sequence of metal links disposed within the dielectric layer. An end metal link of the sequence of metal links is grounded. A change of relative brightness of the dielectric layer proximate to the sequence of metal links is detected. The change of relative brightness comprises a difference between a first brightness associated with a first metal link and a second brightness associated with a second metal link coupled to the first metal link. The change of relative brightness is associated with a defect of the integrated circuit.

Abstract: A method (10) for determining a frequency hopping sequence for a newly-entering network. The method comprises the step of scanning (16) a plurality of frequency channels. For each of the plurality of frequency channels, the scanning step comprises detecting whether a signal (18, 22) exists on the channel and recording information (20, 24) corresponding to each channel on which a signal is detected. Finally, and responsive to the recorded information, the method forms (30) the frequency hopping sequence.

Abstract: The invention relates to bandgap reference voltage generator circuit including a first bipolar transistor and a second bipolar transistor, a first resistor connected so that the voltage drop across it corresponds to the difference between the base/emitter voltages of the two bipolar transistors, and which is located in the collector current path of the second transistor, and a second resistor located in the collector current path of both transistors.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. An embodiment of a processor core is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks.

Abstract: A dichroic spiral color wheel (108) having many spiral-shaped color filters (206). The boundary between adjacent color filters follows the spiral of Archimedes, defined as r=a&thgr;, where r is the radius of the boundary at a given point, a is a constant, and &thgr; is the angle between a radial line through the given point and a reference radial. Using the spiral of Archimedes provides a boundary between adjacent color filters that is nearly parallel to the rows or columns of the modulator and moves across the light path at a constant speed. These two features make the spiral color wheel much more efficient than color wheels having pie shaped segments. The use of dichroic filters, which reflect out of band light is crucial to the operation of a sequential color recycling display system.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). Th method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) with a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) with a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate ({tilde over (S)}1) in response to the first and second estimate signals and the first and second input signals.

Abstract: An amplifier with a electrically controllable gain and enhanced protection against an overload condition is disclosed. The amplifier contains a buffer amplifier configured to convert an input voltage signal to a current signal and an output amplifier that converts a current signal to an output voltage signal. The gain of the amplifier can be controlled by an internal resistor that can be electrically configured to different resistance levels. The amplifier also includes a clamping network used to clamp the output amplifier to prevent an overload condition. This network may take the form of a diode network. Such an amplifier may take the form of a differential amplifier.

Abstract: A photodiode sensor (25) has a photodiode (30) with an associated capacitance (34), which may be a parasitic capacitance of the photodiode (30). A switch (36) is provided for charging the capacitance (34) to a predetermined reset voltage (Vreset), such that when light impinges upon the photodiode (30), the voltage on the capacitance (34) discharges in a time proportional to an intensity of the light. A circuit (42) is also provided for measuring the time for the capacitance (34) to discharge to a predetermined threshold value (33), which may be a function of time. The voltage on the output (38) of the comparator (28) may be sampled, with the sampling period also being variable as a function of time. The image may be reconstructed from time data indicating the relative times that discharge voltage of the pixels in an array cross the reference voltage (33).

Abstract: A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element (53, 153, 203) is coupled between the first and second contact elements (51, 151, 201). At least a majority of the fusing element (53, 153, 203) comprises silicided material.

Abstract: A DC-DC converter that does not need a series resistance element on the output side, and can make use of the parasitic resistance of a coil to improve output characteristics and prevent a decrease in efficiency. In switching unit 40, transistors M1 and M2 are turned ON/OFF alternately in correspondence with pulse signal Sp; input voltage Vin is fed intermittently to node ND1; in output filter unit 10, output voltage Vout that is smoothed with coil Le and capacitor Cout is output to terminal Tout. In feedback control unit 100, divided voltage Vo1 obtained by dividing the voltage at node ND1 is compared with reference voltage Vref, and the result of the comparison is integrated to generate control voltage Vc. In PWM modulation unit 30, pulse signal Sp with pulse width controlled is generated according to control voltage Vc and sent to switching unit 40.

Abstract: A sample and hold device is provided in which sample switches are employed to switch between a sample phase and a hold phase. The sample and hold device provides alternate paths for the AC currents flowing to and from the sampling capacitor during the sample phase to mitigate the deleterious effects of the high AC currents through sample switches. The current drawn by the sampling capacitor from the input signal is replicated and directed to charge and discharge the sampling capacitor through alternate paths with respect to a path through the sample switches.

Abstract: A precision operational amplifier operating in single supply mode, including a single differential transistor input pair and a cascoded CMOS transistor pair, stabilizes the drain-to-source voltage of the input transistor pair to ensure a stable off-set voltage and increased power supply and common mode rejection. The precision amplifier biases the cascoded CMOS transistor pair in accordance with the stabilized drain-to-source voltage of the differential transistor input pair. Such biasing may take the form of body biasing or biasing the gates of the cascode CMOS transistor pair to ensure that the CMOS transistor pair remain in the active region of operation when the common mode supply voltage approaches zero.

Abstract: An assembly and method for improved scanning electron microscope analysis of semiconductor devices include a structure including a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV, and at least part of the surface of the structure coated with a material composed of Iridium, wherein the coating is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.

Abstract: In situ nitridation of a thin layer of either silicon or tungsten provides an adhesive layer for bulk deposition of tungsten. Alternatively, a thin layer of silicon can be deposited directly on a dielectric, then reacted with WF6 to replace the silicon with tungsten, which provides a nucleation layer for bulk tungsten deposition.

Abstract: A hardware latch for limiting access to protected system memory. An N-bit bus provides the instructions executed by the system to a combinatorial logic block (204). The combinatorial logic block (204) provides eight separate outputs and functions as a series of comparators. One input of each comparator is connected to the instruction bus, the other input of each comparator is hardwired to indicate the pattern that appears on the bus when a particular instruction is executed. The output from a given comparator is active when that particular instruction is applied to the instruction bus (202). A counter (208) counts the instructions and selects which output from the combinatorial logic block should be selected by multiplexer (206). If the output of the multiplexer is logic false, the sequence of instructions is broken and the counter (208) is reset. If the output of the multiplexer is logic true, the counter is allowed to continue incrementing.

Abstract: A circuit breaker (10) has a current carrying bimetallic element (18) which bends upon self-heating and upon being subjected to a selected overload current transfers motion to a connecting plate (32) which displaces a latch surface (42b) from a catch (34a) of a bell crank mechanism (34) allowing a spring biased operating member (28) to move movable contact means (12) out of contact engagement with stationary contact means (14) thereby tripping the circuit breaker. An arc sensing circuit (52) is coupled to the load circuit and upon sensing selected arcs causes an arc responsive actuator (56, 62) to be energized to transfer motion to the latch (42) to trip the circuit breaker.

Abstract: A method of generating transistor scattering parameters employs a single circuit simulation with a self-correction scheme for the artificial DC voltage dropped across the 50-Ohm resistor representing transmission line impedance. A sub-circuit without 50-Ohm transmission line resistance is used to compute transistor bias current via a current-controlled voltage source to compensate for the DC voltage dropped across a 50-Ohm resistor contained in the network.