Abstract: Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include picking and removing all of the bad parts from a wafer before picking the good parts and picking all of the good parts first without picking any part necessary to align the wafer. The equipment includes several embodiments of a transfer machine that accommodates the efficient transfer of semiconductor parts between tacky film, waffle packs and tape and reel containment systems. Residual good parts are stored in waffle packs and can be subsequently reused in the packaging process.

Abstract: A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

Abstract: A method and system for indirectly measuring the tilt angle of micromirrors in a micromirror array. The method and system aims a coherent light beam through an aperture in a screen so that it reflects off of the surface of the micromirror array and creates a pattern of reflected light on the screen. The micromirror array is loaded with a pattern that has a uniform power spectral density (such as a random, aperiodic pattern or a frequency chirped sinusoidal spatial pattern) whereby certain micromirrors will be placed in the “on” position and the other micromirrors will be placed in the “off” position. By loading the micromirror array with a pattern having a uniform power spectral density distribution, the discrete nature of the resulting diffraction pattern is reduced and a pair of [sin(x)/x]2 patterns will be generated on the screen.

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transistor may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: A heat dissipating flip-chip Ball Grid Array (BGA) (10) including a substrate (12), a die (14), a first set of solder balls (16) coupling the die with the substrate, a thermal compound (20) attached to a backside of the die, a second set of solder balls (28) attached to the substrate, and a printed circuit board (22) that includes a heat dissipating metal (24). The heat dissipating metal is in contact with the thermal compound, and the second set of solder balls is connected to thermal vias in the printed circuit board.

Abstract: The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decision capability is employed. This technique facilitates the process of setting up complex transfers without risking brute force inefficient processor cycles. Annulment determination allows detection of cases when a set of data cannot be output immediately and the destination pipeline postpones execution of the write command.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: A memory which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.

Abstract: To correct non-linearity and noise in the conversion of a pulse code modulated signal (PCM) into a uniform pulse width modulated signal (UPWM), a model is made of the known non-linearity in the conversion by dividing a plurality of non-linearity components in the model, where the polynomial components are separately weighed with filter coefficients. The model is used as a basis for the construction of a filter of the Hammerstein type whose non-linear parts consist of a division of the PCM signal into a plurality of powers, and whose linear parts are approximated by means of the model made. With the circuit of the invention it is now possible to construct a purely digital amplifier which has a great efficiency, low weight, etc.

Abstract: One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.

Abstract: A network configuration (10) including a first network medium which is a 1394 network as well as a second network medium. Each of the first and second network media is coupled to a corresponding plurality of host-computers (H1 through H3 and H5 through H7). The network configuration further includes a link layer gateway computer (H4) coupled to both. the first network medium and the second network medium. The link layer gateway computer is operable to communicate a data packet from a source host computer selected from one of the plurality of host computers coupled to the first network medium to a destination host computer selected from one of the plurality of host computers coupled to the second network medium.

Abstract: An improved method for forming a contact well for a semiconductor device (10) is disclosed. According to this method, a first insulator layer (24) comprising an insulating material is formed around a gate (20). A contact well filler (32) is then formed adjoining the first insulator layer (24). A second insulator layer (34) comprising the insulating material is formed around the first insulator layer (24) and the contact well filler (32). The contact well filler (32) is then removed to form the contact well (36) in the second insulator layer (34). This method allows the use a non-hazardous selective etchant to form the contact well. The semiconductor device (10) formed in accordance with the present invention also exhibits low parasitic gate capacitance, high switching speed and low power consumption.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

Abstract: The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the substrate and under the membrane and a pillar to support the membrane after the pulldown threshold has been reached. A voltage greater than a pulldown threshold is applied between the membrane and the pulldown electrode will pull the membrane down to make a capacitive coupling to the first conductor. The addition of the pillars increases the upward restoring force when the activation voltage is removed.

Abstract: An analog or continuous tuning loop which generates an analog signal representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to other such trans-conductor circuits used in a filter) and a reference circuit. The analog signal is used to adjust the trans-conductance such that the current generated by the trans-conductance circuit equals a reference current generated by the reference circuit. A filter using such trans-conductor circuits may be designed to be tuned to a desired cut-off frequency when the desired trans-conductance is achieved. An additional digital circuit generates a few digital bits, which may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter.

Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.

Abstract: A system and method for decoupling capacitance for an integrated chip includes a load coupled between a power supply line and a ground. A distributed resistive-capacitive (RC) filter is coupled between the power supply line and the ground in series with the load. The distributed RC filter is operable to provide decoupled capacitance to the integrated circuit chip.

Abstract: On improved transformation method uses an initial set of Hidden Markov Models (HMMs) trained on a large amount of speech recorded in a low noise environment R to provide rich information on co-articulation and speaker variation and a smaller database in a more noisy target environment T. A set H of HMMs is trained with data provided in the low noise environment R and the utterances in the noisy environment T are transcribed phonetically using set H of HMMs. The transcribed segments are grouped into a set of Classes C. For each subclass c of Classes C, the transformation &PHgr;c is found to maximize likelihood utterances in T, given H. The HMMs are transformed and steps repeated until likelihood stabilizes.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.