Abstract: A microactuator, or micromotor, (60) and method for making it are presented such that a symmetrical build up of material is performed on opposite sides of a substrate. This reduces mechanical stresses in the device. In its construction, respective layers of circuit portions (108, 110) are built on each side of the structure, thereby eliminating the need to stack complex patterns. Stacking one complex pattern on top of a similar pattern is difficult because the surface, which is the base for subsequent layers, is not flat. The photolithography process that forms these patterns is not very forgiving to non-flat surfaces. Avoiding the stacked layers also allows thicker conductors to be considered for each circuit. Thicker circuits increase current carrying capacity, which in one of the key variables increase the power of the micromotor.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: A method and apparatus for measuring the transient behavior characteristics of individual micromirrors in a DMD micromirror array. The method and system use sampling techniques to measure an amount of light reflected by an individual micromirror as the entire micromirror array is stimulated with a pattern of alternating driving signals. Sampling is achieved by illuminating the DMD micromirror array with a high-speed illumination source that provides stroboscopic light flashes of very short time length. By synchronizing the light flashes with the mirror driving signal and measuring the amount of light reflected by the individual micromirrors at different points in time, the transient behavior characteristics of individual micromirrors in a DMD micromirror array can be measured with a high level of accuracy.

Abstract: The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods are provided for deterministically generating self-inverting turbo code interleavers from a specification for an existing non-self-inverting interleaver. Methods are also provided for randomly generating self-inverting turbo code interleavers. The present invention also provides methods and apparatus for encoding digital data and communicating the digital data using self-inverting turbo code interleavers/de-interleavers.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critcal width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: Multiple fuse circuits are used associated with a corresponding number of bits forming a desired value which may need to be stored in a non-volatile storage. Assuming the desired value contains a first count number of zeros and a second count number of ones, the fuse circuits at bit positions having values equaling the logical value with smaller count are blown. If the blown fuse circuits generate the logical value associated with larger one of the two counts, the outputs of all the fuse circuits are inverted. Thus, a desired value can be always generated while reducing the number of fuse circuits blown.

Abstract: Optical network dispersion compensation with adaptive dynamic optical filters which relate magnitude and phase of multichannel optical signals.

Abstract: An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 through EC45). For any of the plurality of scan channels having a number of scan elements greater than one element, the scan channel comprises a first element in the scan channel and a last element in the scan channel. For any of the plurality of scan channels having a number of scan elements equal to one element, the one element is both a first element and a last element in the scan channel. Further, selected ones of the scan elements are coupled to affect operation of the combinational circuitry. The integrated circuit further comprises circuitry (24) for coupling a predetermined pattern into the first element of each of the plurality of scan channels and circuitry (26) for detecting the predetermined pattern in the last element of each of the plurality scan channels.

Abstract: Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Abstract: Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.

Abstract: A nulling amplifier (52A) for an auto-zeroed amplifier includes a first differential stage including first (3) and second (16) input transistors and a second differential stage including first (18) and second (19) nulling transistors coupled to drains of the second and first input transistors and to a folded cascode circuit (48) coupled to an output stage (59). A gain boost circuit increases the output impedance of the nulling amplifier. The gm ratios of the first and second input transistors and the first and second nulling transistors have values which establish a predetermined low input-referred noise level in the nulling amplifier, and the gain boost circuit maintains a low offset voltage.

Abstract: A processing apparatus for use in spread spectrum communications includes a controller, a filter programmed in the controller, and a dot product hardware unit external from the controller having the programmed filter. The controller provides a filter input to receive I and Q pilot symbols and a filter output to provide I and Q pilot symbol estimates based on the I and Q pilot signals. The dot product hardware unit has a first input coupled to receive the I and Q pilot symbol estimates, a second input coupled to receive I and Q data symbols, and an output to provide results of a dot product function between the I and Q pilot symbol estimates and the I and Q data symbols.

Abstract: An external direct memory access unit includes an event recognizer recognizing plural event types, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized transaction processor. The service request parameters include a priority for centralized transaction processor independent of the event recognition priority. The service request parameters may be stored in the form of a linked list. The service requests are preferably direct memory accesses which may include writes to the parameter memory for self modification. The centralized transaction processor may signal an event to event recognizer upon completion of a requested data transfer.

Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

Abstract: An alignment tool (300) designed to replace a high-powered lamp with a low-powered lamp to facilitate safe alignment of a projector lamp console. The alignment tool (300) comprised of a cathode portion (302) and an anode portion (304) connected by one or more rods (306). The alignment tool holds a light source such as a flashlight (324) having an exposed bulb (320) in the approximate location of the arc of the high-powered lamp. The cathode and anode sockets and the reflector of the projector lamp console are adjusted until the exposed bulb (320) is at the F1 focal point of the reflector and the optical axis of the alignment tool is the optical axis of the reflector.

Abstract: An improved system for testing the operation of component modules and the interconnections therebetween of an integrated circuit (10) formed on a semiconductor chip is provided which consists of several component modules, each with an associated input scan cell (76) and output scan cell (102) when necessary. A component module may have both an input scan cell (76) and an output scan cell (102) unless the input or output of that component module occurs on the boundary of the integrated circuit (10). Each output scan cell (102) has a mode select signal (122) which indicates either input test mode or output test mode. The improved scan test system uses two process steps to verify the operational integrity of the entire integrated circuit (10). During the first step of the scan test, non-adjacent component modules have their mode select signals set to output test mode, and component modules existing between the non-adjacent component modules have their mode select signals set to input test mode.

Abstract: A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Abstract: A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. The system and method improve the alignment of the micromirror array to the display system by using a consistent set of precision reference regions. The micromirror package substrate 700 engages an alignment fixture portion of a die mounter 702 during the die mount operation, and a similar fixture when installed in a display system. The package substrate 700 is held by the predefined regions on two edges and the three predefined regions on the top surface. When mounting the device in the package optical techniques may be used for x-y plane alignment. Spring plunger 710 biases the substrate against the contact points 708 on the top surface. In the display system or other end equipment, a socket contacts the same six points to align the device.

Abstract: A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current.

Abstract: One particular data sequence generator for spread spectrum communications includes a first data access module, a second data access module, and a binary counter for use in repeatedly providing counter values from 0 to 215−1 at a 15-bit output. The first data access module, which may include a read-only memory (ROM), has first and second pseudorandom noise (PN) sequences encoded therein, each having a length of 215. The first data access module has a 15-bit input coupled to the 15-bit output providing the counter values. The first, data access module also has a first bit output to provide a selected PN bit of the first PN sequence and a second bit output to provide a selected PN bit of the second PN sequence responsive to each one of the counter values from 0 to 215−1. The second data access module, which may also include a ROM, has an N-bit input coupled to N lines of the 15-bit output.