Abstract: A family of optical switches. Each switch (400) includes a holder block (402) to hold optical fibers (410, 412) and ferrules (414) in alignment with a micromirror array (406). The holder block 402 has a reflective bottom surface (404). The bottom surface (404) functions as a retro-reflector when the optical switch (400) is assembled. The micromirror array (406) has a substrate on which rows of micromirrors have been fabricated. The ferrules (414) are held at an angle relative to the micromirror array (406). This angle allows the light emitted from the input fiber (410) to traverse the array of micromirrors (406) to the output fiber (412). Light from the input fiber (410) is reflected between a series of mirrors (408) and the retro-reflective surface (404) until reaching the output fiber (412). The rotation of the mirrors determines the path of light across the mirror array (406) and which output fiber (412) the light reaches.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C.

Abstract: A processor, comprising a monitor for measuring the relative amount of Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor. Another embodiment discloses a processor, comprising a monitor for measuring the relative importance of Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of said processor. Still another embodiment discloses a processor, comprising a monitor for measuring the relative amount of time between Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor.

Abstract: An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.

Abstract: An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a ‘1’ for the purpose of removing ‘rogue’ character sequences; otherwise it is always set to a ‘0’.

Abstract: A pressure switch 1 of this invention comprises a base electrode 2, a terminal 3, a disc 4 and a diaphragm 5. The base electrode 2 has a switching chamber 7 for inserting the contact part 3a of the terminal 3. The switching chamber 7 is sealed with an insulation member at one side. The disc 4 is formed so as to be able to contact with the contact part 3a of the terminal while it is connected to the base electrode 2 and to be able to inverse under a predetermined magnitude of pressure. The diaphragm 5 is made of a metal and is fixed to the base electrode 2 so as to keep vacuum of the switching chamber 7 including the contact part 3a and the disc 4 by sealing the opening of the switch chamber 7 at other side.

Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.

Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

Abstract: A tuned run-to-run controlled system is disclosed that provides tuned run-to-run control of a system. The system includes a controlled system coupled to a tuned run-to-run controller, which contains a feedback controller coupled to a tuner. Tuned run-to-run controller determines a feedback command based on a nominal gain, a maximum gain, a process error, and a tuning gain.

Abstract: A mass data storage device system (70) and method for providing frequency compensation within it are disclosed. The system has a moving media (72) that contains signals encoded in oriented magnetic domains that are detected by a magneto-resistive head (78) positioned in proximity thereto. An amplifier stage (100 or 120) is connected to sense the change in the electrical characteristic of the head, and capacitors (102-105 or 126-131) are operatively connected within the amplifier stage to produce two or three poles in a frequency response of the amplifier stage to reduce a second order frequency response of the head. Preferably, the poles have substantially identical pole locations.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively deposited onto the cobalt silicide layers (118, 120, 122). The semiconductor device (100) is annealed to form disilicide layers (130, 132, 134) from the cobalt silicide layers (118, 120, 122) and the silicon contained in silicon regions (104, 106, 108) and silicon layers (124, 126, 128).

Abstract: A method and apparatus to make the signal slice level during data qualification in an Optical Disc apparatus adaptable to DSV variation. According to this method, phase error signals from a Phase Locked Loop (PLL) subjected to the input data signal are used to generate Pump Up (PU) and Pump Down (PD) signals. These signals are used to determine a direction and degree of a slice level shift and to control a voltage adjustment, by feedback, of the modulated input analog signal to compensate for the slice level shift. The present invention also adapts to the presence of non-zero DSV, or DC components, by generating phase error signals (also by the PLL) when DC components (and corresponding DSV variation) are detected. When DC components are detected, slice level shift is cancelled. In this manner, the method suppresses a system response to any effects of DC component variation and thereby adapts to their presence.

Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.

Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.

Abstract: A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is nearly removed, a drop in voltage indicates thinning of the film which detects endpoint for etching before optical emission techniques. The voltage drop is measured across resistors within the matching network.

Abstract: A wireless network is disclosed in which individual wireless stations can be configured to implement any of a plurality of physical configurations including antenna configurations. Such antenna configurations may include, without limitation, multiple input multiple output (MIMO) and single input single output (SISO). Different types of MIMO configurations can also be implemented such as open loop MIMO and closed loop MIMO.

Abstract: A circuit and method for providing drive currents to a polyphase dc motor are presented. The circuit (40) includes a circuit for generating a user-defined waveform first. signal in synchronism with a reference frequency signal. A reference frequency signal generator (62) generates pulses of a second signal at a reference frequency. A commutation circuit (56) combines segments of the first and second signals, and a circuit (64) is provided for applying the combined sinusoidal/trapezoidal waveforms to coils of the polyphase dc motor in a commutative sequence. Preferably, the user-defined waveform, when combined with the second signal, has approximately a sinusoidal/trapezoidal waveform.

Abstract: A system for simultaneously securing a plurality of integrated circuits in a test fixture, comprising a base supporting a test board having a plurality of sockets. Each socket is configured to receive a integrated circuit and has a locked position and an unlocked position. The system further comprises a fixture adjacent to the test board and plurality of sockets comprising a support mechanism connected to the base, a contact region coupled to the support mechanism, and a means for moving the contact region to a contact position whereby the contact region, when in the contact position, contacts the plurality of sockets to move the plurality of sockets to the unlocked position.

Abstract: The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1).

Abstract: A digital system is provided with a microprocessor (100), a cache (120) and various memory and devices (140a-140n). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) (130). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit (110) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.