Abstract: Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace infonnation indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.

Abstract: A battery protection circuit includes a moisture detection circuit, a temperature sensing circuit, and a high-temperature battery discharge circuit. The moisture detection circuit includes a pair of conductive traces closely spaced on a substrate such that a resistive path is formed between the traces when moisture forms on the substrate. The traces are connected between the positive battery terminal and a pull-down current source. When moisture forms on the substrate, pull-up current flows between the traces, and a resulting voltage change on one of the traces is detected by circuit element such as a logic inverter. The temperature sensing circuit includes a voltage reference circuit that generates a proportional-to-temperature voltage and temperature-independent voltage reference signals corresponding to various predetermined temperatures.

Abstract: A circuit and method is provided that allows for communication of digital to analog data over more that one channel employing a single current switching DAC and a current switching multiplexer. The current switching multiplexer is an output stage circuit that is used to steer the current from one output channel to another. The data rate of the data transmitted to the DAC is increased by the number of channels that the data is being transmitted over. The data is then switched from one channel to the other by employing a current switching multiplexer, such that the device provides for the same functionality that conventional devices utilizing a single DAC for multiple channels as opposed to a single DAC for a single channel.

Abstract: An analog-to-digital converter receiving an analog input signal (VIN) including an offset component, and includes a switched capacitor input circuit (101) configured to sample the analog input signal (VIN) to produce and store a signal representative of the sampled input signal between a first conductor (17) and a second conductor (27). A conversion circuit (1) is coupled to the first conductor (27) and the switched capacitor input circuit (101) to produce a digital output signal (DATA OUT). An offset correction circuit (4) includes an output coupled to the second conductor (27) and an input receiving a digital offset correction signal (DATA IN), the offset correction circuit (4) including a switched capacitor correction circuit (4A) operative in response to the offset correction control signal (DATA IN) to transfer charge to/from the second conductor (27).

Abstract: A communications device (100) with an extended filter (74) provides more bandwidth for V.34, V.90 and other data communications protocols. The device (100) permits voice and data communications over the same twisted pair connection (22) to a central office facility (35) and allows an increased data rate between a subscriber (15) and the central office linecard (50). A variable frequency filter (74) capable of switching between “voice” mode and “data” mode is used. In “data” mode, the bandwidth of filter (74) is extend to provide more bandwidth which can be utilized to transfer data. A line monitoring mechanism (102) is provided which monitors the PCM data flowing over a digital backplane (60) as well as requests from a subscriber for an increased data rate connection. A micro-controller (104) can be provided to adjust the bandwidth of the filter (74) and cause it to enter “data” mode.

Abstract: Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).

Abstract: Capacitors for integrated circuits with a common polysilicon layer for both MOS gates (274, 276, 278) and capacitor (270) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.

Abstract: A variety of methods of initializing a connection between a remote modem and a central unit in a communication system that utilizes a multi-carrier modulation scheme are described. In one aspect of the invention, a relatively long duration single frequency activation signal that ramps up and ramps down in intensity is utilized. In a preferred embodiment, the activation signal is transmitted on a sub-carrier that is outside a range of sub-channels used for data transmission in the multi-carrier modulation scheme. In a separate aspect of the invention, an initialization sequence that includes central synchronization signal, a remote synchronization signal, a central setup signal, a remote setup signal, a central setup complete signal a remote message and a central message. The central unit transmits a central setup complete signal when it has completed a central setup procedure.

Abstract: A wafer-scale assembly apparatus for integrated circuits and method for forming the wafer-scale assembly. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dieletric sidewall spacers.

Abstract: The invention described is a method of forming an improved dielectric material by adding lead to an original perovskite material having an original critical grain size to form a lead enhanced perovskite material, then forming a layer of the lead enhanced perovskite material having an average grain size less than the original critical grain size whereby the dielectric constant of the layer is substantially greater than the dielectric constant of the original perovskite material with an average grain size similar to the average grain size of the layer. The critical grain size, as used herein, means the largest grain size such that the dielectric constant starts to rapidly decrease with decreasing grain sizes. Preferably, the lead enhanced perovskite material is further doped with one or more acceptor dopants whereby the resistivity is substantially increased and/or the loss tangent is substantially decreased.

Abstract: An inverted MOSFET process. A replacement gate (100) and removable sidewalls (80) allow the formation of spot implant regions (120) and (130) to form the pocket region (120) and the drain and source regions (130) of the MOSFET. The replacement gate (100) has a flared profile for reduced resistance.

Abstract: An offset error compensation system is provided that includes a comparator (42) having an offset error (44), a positive receptor (56), a negative receptor (58), a positive output (60), and a negative output (62). A sequence generator (14) generates control signals (22) representing normal cycles and swap cycles. A first cross connect (46) is coupled to the positive receptor (56), the negative receptor (58), a positive input signal (52), and a negative input signal (54). The first cross connect (46) couples the positive input signal (52) to the positive receptor (56) and the negative input signal (54) to the negative receptor (58) in response to a normal cycle. The first cross connect (46) further couples the positive input signal (52) to the negative receptor (58) and the negative input signal (54) to the positive receptor (56) in response to a swap cycle. A second cross connect (48) is coupled to the positive receptor (56), the negative receptor (58), the positive output (60), and the negative output (62).

Abstract: A high-impedance current source 100 having an enhanced compliance voltage. The current source 100 preferably has a means for generating a biasing current 105 and a first current mirror stage having a first transistor M6 coupled to a second transistor M1. A second current mirror stage having a third transistor M2 coupled to a fourth transistor M5 acts as a feedback circuit. A stabilization circuit having a fifth transistor M3 coupled to a sixth transistor M4 are also included. The stabilization circuit is coupled between the first and second current mirror stages and an output circuit having a seventh transistor M7 is connected to the stabilization circuit between the first and second current mirror stages. The current mirror circuit has a low compliance voltage, enhanced operating characteristics and enhanced dynamics which eliminate the need for OTAs.

Abstract: This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the portions corresponding to a desired pattern 36 of an energy source 42; and selectively forming build-up layers 66,68 over the prenucleated portions to form a mask over the structure to be patterned. Other methods are also disclosed.

Abstract: In a sealed casing (2) there are provided a bimetal disc (8) which carries out the switching of an electric current path by snapping between oppositely dished configurations in conformity with the level of the electric current that flows therethrough and ambient temperature by moving a movable contact (10) into and out of the electric current path. A fuse terminal (14, 15, 141, 142, 143, 144) is connected in series with the bimetal disc (8) and shuts off the current path by being melted by an over-current. The fuse terminal (14) in one embodiment is fixed on one surface of a support member (3) that serves as a heater. The fuse terminal (14) and the bimetal disc (8) are connected through a connective pin (12) which is provided through the support member (3) electrically insulated therefrom. In another embodiment the bimetal disc (8) and the fuse terminal (15) are disposed on opposite face surfaces of support member (3).

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: An in-range fault detection system for a full wheatstone bridge element (12) having piezoresistive elements (R1, R2, R3, R4) has bridge outputs (INP, INM) connected to measuring means in the form of a first circuit portion (13) to provide a common mode voltage (VCM). A second circuit portion (14) is used to provide a centering voltage (C*VBRG) equal to the common mode voltage at the time of sensor calibration and a third circuit portion (15) is used to provide a small window voltage (W*VBRG) which is a fraction of bridge voltage. The value (W*VBRG) is subtracted from (C*VBRG) at a first summing circuit (SUM1) and added to (C*VBRG) at a second summing circuit (SUM2) and the results are each compared to the common mode voltage by comparators (Q1, Q2) which are then determined to be within or without a window of valid values by an OR gate (Q3).

Abstract: For PCM upstream, the analog modem must transmit a filtered sequence of symbols so that the samples of the signal at the input to the codec at the central office (CO) are at a predetermined set of levels. This requires that the analog modem use an 8 kHz symbol rate synchronized to the CO clock. Typical telephone channels have nulls at DC and at 4 kHz. Therefore, for best performance, the signal transmitted by the analog modem should be spectrally shaped to match the channel. The present invention utilizes a generalized Laroia-Tretter-Farvardin (LTF) precoder similar to the one used in V.34. This precoder structure allows spectral shaping and could also allow for constellation shaping gains. Using this precoder structure with spectral shaping has the potential to improve data rates by 3-3.5 kbps.