Abstract: A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.

Abstract: A DC converter to connect a first DC voltage to a second DC voltage includes a first switch connected to input the first DC voltage, a second switch connected to the first switch, the first switch and the second switch generating a first main voltage, a third switch connected to the first switch, a fourth switch connected to the third switch, and a latch circuit to control the third switch and to control the fourth switch.

Abstract: The present invention relates to a hysteretic dc-dc converter circuit comprising a buck converter circuit having an output which forms an output of the converter circuit and a hysteretic comparator circuit having an output coupled to an input of the buck converter circuit and a first input coupled to the output of the converter circuit. The converter circuit also comprises a feedback circuit coupled between the output and a second input of the hysteretic comparator circuit. The feedback circuit generates a feedback ramp signal which is a function of an output of the hysteretic comparator circuit and which is out of phase with respect to the output of the converter circuit. The output feedback coupled with the ramp signal feedback provide for an increased hysteretic comparator trip frequency, thus increasing a natural frequency of the converter circuit without requiring an alteration of the hysteretic window.

Abstract: A circuit (43) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines (40) are coupled to the signals, each tapped delay line including a plurality of delay elements (42) and having a plurality of exit points (E) through which said signal may propagate. A test circuit (20) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.

Abstract: A phase alignment circuit which will take a square wave of constant period but indeterminate duty cycle and will transform it into a square wave of equal period and deterministic duty cycle, e.g. 50%. The preferred embodiment alternately charges and discharges two equal capacitors, and passes the resulting ramp voltages through a comparator to produce a square wave output with a 50% duty cycle.

Abstract: A double sided electrical connection flexible circuit particularly useful as a substrate for an area array integrated package, and the method of fabricating the structure is described. A circuit having interconnections on one surface and solder ball contact pads on the second surface are interconnected by copper plated from a single surface in order to avoid entrapment of air pockets. In one embodiment, the conductive vias are formed from a copper film which extends from the solder ball contact pads, which may be indented, providing a well for solder balls in the contact pad.

Abstract: The present invention relates to a single-to-differential signal transformation circuit which comprises a differential signal generation circuit which is operable to receive a single-ended signal and generate a pair of differential signals having a phase relationship associated therewith. The transformation circuit further comprises a phase analysis circuit operably coupled to the differential signal generation circuit which is operable to ascertain the phase relationship between the differential signals and generate a status indication associated therewith. In addition, a compensation circuit is operably coupled to the phase analysis circuit and is operable to alter a function of the transformation circuit based on the status indication from the phase analysis circuit such that the altered function causes the phase relationship of the differential signals which form a circuit output to be closer to 180 degrees than an initial phase relationship generated by the differential signal generation circuit.

Abstract: A semiconductor wafer is disclosed comprising a substrate having a surface carrying an array of integrated circuit chips bordered by dicing lines; at least two sets of substantially parallel structures within each of said dicing lines, each set extending along the edge of a chip on opposite sides of each dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively, and a sacrificial composite structure in combination therewith, between said wall and the center of the dicing line, said composite structure including means of dispersing the energy associated with crack propagation, whereby any crack having sufficient energy to penetrate the composite structure will be transformed into a plurality of weaker cracks, non of which will be capable of penetrating said wall.

Abstract: A class AB output stage includes an amplifying stage adapted to produce first (9) and second (10) output signals which incrementally increase and decrease in response to an incremental increase and decrease, respectively, of a first input signal (Iin1) and/or a second input signal (Iin2) A gate of a pull-up transistor (14) is coupled to receive the second signal (10), and a gate of a pull-down transistor (12) is coupled to receive the first signal (9). A first feedback circuit includes a first current sensing transistor (11) having a gate and source connected to the gate and source, respectively, of the pull-down transistor (12) and a drain coupled to a first control input (7) of the amplifying stage and operative to increase the gate voltage of the first current sensing transistor (11) only until its drain current increases to a first predetermined value representative of a minimum desired quiescent current in the pull-down transistor (12).

Abstract: A fast FIFO memory system stores identical data in both static RAM memory and FIFO memory. Data is transferred from the FIFO when insufficient RAM read time is available. When the FIFO is full, additional data is stored in the RAM which runs at a much slower speed than the FIFO. Data is then transferred from the RAM until the FIFO is no longer full, at which time the memory system again functions at the faster FIFO speed.

Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Abstract: A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface including at least one dimple having a suitable size and shape to receive a solder ball or solder paste; and said dimple having an electrically conductive solderable surface connected to said terminal.

Abstract: The present invention is a digital transmissions receiver system which includes digital transmissions receiver (10) and correlation co-processor (12). Optionally, an additional memory device (14) for storing input and output buffers may also be included. Communications between the digital transmissions receiver (10), the correlator co-processor (12), and the optional memory device (14) are carried out over co-processor interface (16). The correlation co-processor (12) performs correlation operations at the request of the digital transmissions receiver (10). Power consumption in the correlation co-processor (12) is reduced by performing the requested correlation operations in stages. The number of stages used is inversely proportional to the number of gates required to implement the correlation function. Thus, the more stages used, the fewer gates required. This, in turn, provides lower power consumption as compared with a non-staged implementation of the correlation function.

Abstract: A method of controlling the transmission amplitude of signals in a DMT communications system limited by a predefined dynamic range is disclosed. A block of bits is converted to a set of M constellation points in the fourier domain. The M constellation points are then mapped to a set of N complex points, wherein M is less than N, the N complex fitting within transmission subspace of the dynamic range of the system.

Abstract: A packaged semiconductor device with electrical redundancy for improved mechanical reliability and a method for fabrication are disclosed. The device comprises a semiconductor chip having an integrated circuit, said circuit having a multitude of electrical terminals with metal contact pads; an interposer of electrically insulating material having electrically conductive paths extending through said interposer from one surface to the opposite surface forming electrical entry and exit ports on said insulating interposer; said interposer with its entry and exit ports having regions of different mechanical stress levels; each of said chip contact pads being electrically connected to a respective entry port of said interposer and by means of said conductive paths to at least one respective exit ports; and at least one of said entry ports being electrically connected to a plurality of high-stress exit ports in parallel.

Abstract: An embodiment of the instant invention is a method of depositing a TiN-based film over a semiconductor wafer, the method comprising the steps of: substantially simultaneously subjecting the semiconductor wafer to TiCl4, H2, and N2; and subjecting the semiconductor wafer to a plasma, such that the combination of the TiCl4, H2, and N2 and the plasma cause the deposition of a TiN based film to form over the semiconductor wafer. Another embodiment of the instant invention involves additionally subjecting the semiconductor wafer to SiH4 so as to form a TiSixNy film over the semiconductor wafer. Another embodiment of the instant invention involves additionally subjecting the semiconductor wafer to B2H6 so as to form a TiNxBy layer over the semiconductor wafer.

Abstract: An improved write drive circuit which provides an adjustable writer drive current and overshoot transient for a H-bridge drive circuit in a hard disk drive. The invention uses a variable capacitor circuit to give an initial boost to the write driver transistors. In a preferred embodiment, the capacitance of the variable capacitor is controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: An adaptive equalizer capable of tracking rapid channel variations while maintaining high stability and low jitter, and a receiver constructed therefrom. A novel feature of the invention is that is that the equalizer is sectioned, that is constructed from a plurality of feed-forward sections and decision-feedback sections, where these sections comprise a cascade of an adaptive linear filter and an adaptive multiplier. This structure is effective at combating rapid channel variations, which are a result of delay variations of the reflections of the signal, e.g., airplane flutter, without sacrificing the stability and the accuracy of the equalizer even in cases where the equalizer has a large number of taps. The different equalizer sections may have different step size parameters. A controller monitors the channel variations and adjusts the step size parameters of each section accordingly.

Abstract: A tunable high voltage trigger silicon controlled rectifier (SCR) with a high holding voltage is disclosed. The source of a drain extended MOS serves as the remote cathode for the SCR, while the drain of the drain extended MOS serves to generate avalanche currents to trigger the SCR.

Abstract: A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.