Abstract: A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).

Abstract: To prevent the contact of adjacent wires when a molding resin for forming the external shape of a semiconductor package is poured. The semiconductor device of the present invention is equipped with a semiconductor chip 13 that has a row of electrode pads 13a along the periphery of the principal plane, wires 14 that extend from each of the electrode pads 13a, a molding resin package material 15 that covers at least the above-mentioned semiconductor chip 13 and the wires 14 and that forms the external shape of the semiconductor device, and dam members that are arranged between the two closest of the above-mentioned wires 14a and 14b, which are arranged so that the corners of the above-mentioned semiconductor chip are inserted in between the wires, that is, the dummy wires 17.

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface. Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30). The entire wafer (10) is exposed to a nitrogen ion containing plasma to form a nitrided layer (22). The photoresist (14) is removed, and the exposed portion of the oxide layer (12) is etched to the wafer (10) surface. Finally, an oxidation step forms a silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: A fuse status detection and serial interface programming circuit which provides a current-free method of detecting a fused/non-fused state of a fuse, and which also prevents filament regrowth. The circuit employs an output inverter to monitor the status of the fuse, and switching transistors to initially blow the fuse, and automatically reblow the fuse if filament regrowth appears.

Abstract: A slew rate controlled power amplifier (112) for use in a dc motor driver circuit is presented. The amplifier (112) has a power transistor (72) connected to control a drive current (IMOTOR) in a phase of the dc motor with which it is associated and to develop an output voltage (VOUT) on the phase in accordance with the drive current (IMOTOR). A mirror transistor (74) is connected to establish the ratioed magnitude of the current in the power transistor (72), and a feedback circuit (90) is connected to controllably feed back the output voltage (VOUT) to the mirror transistor (74) to control the drive current (IMOTOR). A commutatively operated slew-rate control circuit (57,58) is connected to the feedback circuit (90) to control the drive current (IMOTOR). By coupling the feedback from the phase voltage, VOUT, into the current loop the loop stability is greatly improved and oscillations on the output phase voltage are reduced or eliminated.

Abstract: A data converter (20). The converter comprises an input (I0-I3) for receiving a digital word. The converter further comprises a string (22) of series connected resistive elements. The string comprises an integer number T of voltage taps (T0′-T8′). The converter further comprises an output (VOUT2) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.

Abstract: A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72) may include forming the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

Abstract: A battery manager that provides the ability to switch multiple batteries, battery cells, or other forms of power sources to power external devices individually, in series, and/or in parallel. The device is typically electronic based and consists of voltage level detecting circuits for comparing each power source to a reference voltage, FET control logic for controlling the switching matrix, and a switching matrix which accomplishes the required configuration of power sources to provide an output power source. The invention can be extended with the addition of an output power monitor, DC/DC converter, and control signals that augment internal switching. Depending upon implementation requirements, the battery manager can be in the form of a single integrated circuit.

Abstract: A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment materia

Abstract: A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.

Abstract: An ammonium or amide aqueous solution without oxidzers for cleaning semiconductor wafers with exposed TiN (103). Effective particulate (109) removal occurs without the standard use of hydrogen peroxide which would attack the TiN (103). Solution temperatures up to 90° C. plus applied ultrasonic energy enhance the cleaning efficiency. Surfactants may be included.

Abstract: A precision wide-range variable delay system whose delay is independent of process, voltage, and temperature variations. A delay controller supplies a voltage, that is independent of process, voltage, and temperature variations, and that is used in a delay line to set the amount of delay through all individual delay elements cascaded together inside of the delay line. The number of cascaded delay elements determines the maximum delay of the delay system. An output voltage controller regulates the output voltage swing of the output from the delay system for stability of the delay over voltage variations. The desired delay from the system is variable and is determined by the user. The pre-delay timing relationships of multiple signals, that are delayed, is maintained by the delay system.

Abstract: A splitterless DSL modem (200) with an integrated off-hook detector (260) prevents data loss and/or disconnections as a voiceband device (154) coupled to the same transmission line (150) transition between steady states. The splitterless DSL modem (200) include a DSP (260), an interface (250) to a twisted pair wire line (150), signal converters (220, 222), and various filters (230, 240). The off-hook detector circuit (260) can be coupled to the interface (250) on the analog side of the DSL modem (200) or on the digital side of the signal converters (220, 222).

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: A low voltage CMOS bus switch (20) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (30) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref2, Dref3) when the supply (Vcc) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN1,MP1) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR1) turns off and a gate voltage of a N-channel pass transistor (MN1) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.

Abstract: Circuitry and method for synchronizing operating speeds of signal processing devices to the data rate of a signal. It applies in particular to Compact Disk (CD) and Digital Versatile Disk (DVD) drives to be used with portable devices. The circuitry does not require clock synchronization speeds in excess of the instantaneous data rate used by the disk drive and also reduces power consumption.

Abstract: A forward impulse response, linear-phase matched filter, receiving as an input a sampled digital representation of an input signal, x(n), having n samples, and providing a filtered output, ya(n), having K stages, stage 0, stage 1, . . . stage k, . . . stage K−2, stage K−1. The implementation of the filter includes a block in stage 0 for multiplying the values x(n) by the value 1 - b 2 1 - bz - 1 to generate values v0(n). Blocks are provided in stages 1 though K−1 for generating the values vk(n) for k=1→K−1, where vk(n)=bvk(n−1)+vk−1(n−1)−bvk(n). Further blocks are provided in stages 0 through K−1 for multiplying vk(n) by a respective constant value, ck, for generating a series of intermediate values ik.

Abstract: A method of filtering a bath (1,31) having a liquid containing particles of varying sizes therein and the recirculation and filtering system. The method and system require providing a recirculation route from the bath outflow and returning to the bath inflow. The route includes a first path communicating with the bath outflow and having serially a first controllable valve (5,9) and a filter having a relatively large pore size. The route also includes a second path communicating with the bath outflow and having serially a second controllable valve (11,15) and a filter having a relatively small pore size. There is a return path from each filter to the bath inflow. The return path from each filter can be a separate path or the paths can be connected at the output end before returning to the bath.

Abstract: An analog-to-digital converter has a binary weighted capacitor array with one plate of each capacitor connected at an input to a comparator and successive approximation logic circuitry provided for selectively connecting the capacitors to high reference, low reference or analog input signal voltage to develop a digital output in a successive charge redistribution conversion process. An on-board test data generator provides a test input voltage signal for a test mode. The other plate of each capacitor is selectively connected to the high or low reference voltage to charge the capacitors separately according to a prestored or externally supplied test pattern sequence. The digital output obtained from applying the usual sample, hold and charge redistribution process to the internally supplied test signal is compared to an expected digital output for an input signal corresponding to the predetermined test pattern sequence.

Abstract: A method for fabricating a memory cell includes forming a first access line (16) for a storage node (140, 210) and forming a second access line (82) operable to access the storage node (140, 210) in connection with the first access line (16). The first access line (16) includes a first terminal (32) and a second terminal (34). The second access line (82) includes a conductive layer (70) connected to the first terminal (32) of the first access line (16). An opening (88) is formed in the second access line (82) for connection of the storage node (140, 210) to the second terminal (34) of the first access line (16). A sidewall (92) is formed in the opening (88) to form a contact hole (94) insulated from the conductor (70) of the second access line (82). The storage node (140, 210) is formed having a self-aligned contact (102) formed in the contact hole (94) and connected to the second terminal (34) of the first access line (16).