Abstract: An apparatus for producing a clock signal includes a recirculating delay-locked loop operable to receive a reference clock signal, produce an output clock signal, and adjust the relative phase, with respect to the reference clock signal, of the output clock signal to align the output clock signal with the reference clock signal. The apparatus also includes a phase filter that is operable to receive the output clock signal and filter any phase shift of the output clock signal over a plurality of cycles of the output clock to produce an adjusted output clock signal.

Abstract: An electric apparatus (10) according to the present invention comprises electrically separated first and second terminals (14, 13), a first contact (16) that is connected electrically to the first terminal (14) within a casing (11), a second contact (15) that is connected electrically to the second terminal (13) within the casing and an operating member (20) for moving the first and second contacts relative to one another. In the present invention, at least the first contact (16) comprises a first conductive layer (41) with a given thickness including a face that is engageable with the second contact, a second conductive layer (42) that is connected to the first terminal (14), and insulating fiber (43) that is interposed between the first and second layers so that the above-mentioned second contact is engaged in the closing contacts movement by the insulating fiber when it is exposed by wear of the first layer (41) due to opening and closing movements of above mentioned contacts.

Abstract: An LFRS (40, 50) calculates a PN sequence using Fibonacci form, such that when an offset is calculated from a known state, the bits of the new state comprise a block of sequence bits. Accordingly, to calculate a block having a length less than the length of the LFSR (40), all bits of the desired block can be calculated in a single offset calculation. If the block has a length greater than the length of the LFSR, one or more additional masks can be used to calculate the additional bits of the block sequence. Zero insertion is also supported.

Abstract: A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.

Abstract: A terminal connector (10, 60, 80, 100, 120, 142) for connecting a lead wire to a terminal which is a component of a current path so that the current path will be established. The terminal connector has a lead wire attachment portion (12, 62, 82, 102, 122, 144) which is fixed to the terminal connector with continuity maintained with respect to the lead wire, a terminal mounting portion (13, 63, 83, 103, 123, 143) mounted on the terminal, a fuse portion (14, 64, 84, 104, 124, 145) which electrically connects the lead wire fixing portion and the terminal mounting portion to each other and which melts at a predetermined overcurrent, and a reinforcement portion (15, 85, 105, 125, 146) which protects the fuse portion against external forces.

Abstract: An improved waveform generator (10) permits digital spectrum spreading by employing circuitry for controlling the charging and discharging of a load capacitor (24) to alter the generator's base frequency. A charge/discharge circuit (22) modulates the currents into the capacitor (24) to effect the slope of the triangle signal waveform (202). A threshold detector (26) determines the amplitude of the base frequency. Switch logic (28) controls an array of 1/N current switches (18) that provide incremental values of a reference source (12) to a summing function (16) which, in turn, feeds a charge/discharge circuit (22). The energy of the triangle waveform (202) remains approximately the same only it is now spread over a range of frequencies with the amplitude of the signal at a given point less than the amplitude of the base.

Abstract: A microprocessor (5) including a plurality of write buffers (30) of varying sizes is disclosed. The varying sizes of the write buffers (30) allow for each write transaction from the core of the microprocessor (5) to be assigned to the most efficient write buffer size. Each write buffer (30) also includes sequential control logic (50) that issues a status code indicating the extent to which its write buffer (30) is filled; the control logic (50) advances to a more full state responsive to receiving a new data transaction from the internal bus, and advances to a more empty state responsive to completing a write transaction to the external bus. Each write buffer (30) communicates data from an internal bus (PBUS) to an external bus (BBUS) in a manner that is synchronized in the control path, rather than in the data path.

Abstract: An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred embodiments include HSQ (140) as the gap filling low dielectric constant insulator and fluorinated silicon oxide (150) as the between metal level low dielectric constant insulator.

Abstract: A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comprising the steps of obtaining active regions in a substrate 10 with gates 30 and 32 for the low voltage device 24 and the high voltage device 26, respectively, obtaining lightly implanted source and drain extensions 38 and 40 for the low voltage device 24, forming a side wall 42, 44, 46 and 48 next to each gate 30 and 32, and angularly implanting each of the source and drain regions 52, 54, 56 and 58 with an impurity 50 of a selected type for both the low voltage device 24 and the high voltage device 26, to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure (step 306 of FIG. 1); forming a photoresist layer over the layer of the dielectric material (step 308 of FIG. 1); patterning the layer of the dielectric material (step 308); removing the photoresist layer after patterning the layer of the dielectric material (step 312 of FIG. 1); and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF4, C2F6, CHF3, CFH3 and other fluorine-containing hydrocarbon (step 313 of FIG. 1).

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: Self-aligned silicidation (e.g., Ti, Co, or Ni silicides) for silicon integrated circuits with an HF-based final etch of the silicide to remove filaments. Either ultradilute HF solution or HF vapor may be used.

Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.

Abstract: A pseudo-inverse derived model-point-to-image-point transformation hypothesis generator as could be used in a computer vision system. Preferred embodiments include generation of n-point transformations directly from n point pair sets and generation of n-point transformations from sets of n point pairs defined by a preliminary three-point transformation plus sets of (n−3) points having minimal error with respect to the three-point trnasformation. Systems include salient corner extraction and hypothesis transformation verification by further sets of point pairs.

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.

Abstract: A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Abstract: A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.

Abstract: A method and apparatus encoding and decoding data for storage on a mass storage device is described. The code used is a 5/6 rate code in which a maximum transition run constraint is imposed. This code is designed for use with an EEPR4 read channel and provides a Euclidian squared free distance, d2free, of 10 when used with an EEPR4 partial response filter and a Viterbi decoder.

Abstract: A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (12) is selected that also has high thermal conductivity. Cavities (14) in the substrate or packaging material (12) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (18) having multiple layers interconnects the one or more semiconductor devices to an array of pads (20) on a surface of the thin film overlay facing away from the substrate or packaging material.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.