Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

Abstract: A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.

Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer is stacked on the first silicon substrate, and N type dopant is in situ doped into the second silicon layer, and then a third silicon layer is stacked upon the second silicon layer. A gate structure is formed by patterning the stacked silicon layers, and source/drain structures with LDD regions are subsequently formed in the substrate by ion implantation processes. Finally, a thermal treatment is performed to form shallow source and drain junction in the substrate, thereby achieving the structure of the CMOS device. Meanwhile, the N type dopant is driven to the boundaries of stacked silicon layers of gate structure so as to act as diffusion barriers for suppressing boron penetration.

Abstract: A cleaning agent for use in producing semiconductor devices. The cleaning agent is an aqueous solution containing (A) a fluorine-containing compound, (B) a salt of boric acid, (C) a water-soluble organic solvent, and optionally, (D) a specific quaternary ammonium salt or (D′) a specific ammonium salt of an organic carboxylic acid or a specific amine salt of an organic carboxylic acid. The polymeric deposit inside and around the via holes and on the side wall of the conductive line pattern formed during the dry etching process can be effectively removed by using the cleaning agent without affecting the dimensions of the via holes and the conductive line pattern.

Abstract: A signal transmission circuit which enables the distance of signal transmission to be increased, while the signal delay and power consumption are reduced. The signal transmission circuit includes a driver circuit, a receiver circuit, an equalizer circuit that flattens the output of the driver circuit, and an intermediate amplifier circuit. The intermediate amplifier circuit is connected to input/output shared terminals in the wiring that connects the driver circuit and the receiver circuit. With the aid of the positive feedback of the intermediate amplifier circuit, a differential signal output from the driver circuit is amplified and then transmitted to the receiver circuit.

Abstract: A method of fabricating a semiconductor device which includes providing a silicon substrate having a patterned mask thereover to expose a portion of the surface of the substrate. The exposed surface portion is oxidized to form a sacrificial silicon oxide region to a predetermined depth in the substrate at the exposed portions of the substrate. The sacrificial silicon oxide is then removed by a HF etch and a second region of silicon oxide is formed in the substrate in the region from which the sacrificial silicon oxide was removed. The step of removing the silicon oxide also includes removing a portion of the pad oxide. The sacrificial silicon oxide has a thickness less than the second region of silicon oxide which is from about 10 percent to about 30 percent of the thickness of the second region of silicon oxide. The oxidation steps are thermal oxidation steps in an oxygen-containing ambient.

Abstract: A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Abstract: The list of priorities which include both planner goals, and scheduling goals are employed to produce a global production list of goals. The goals list is used to resolve a choice.

Abstract: The output edge control circuit includes: a high side transistor 27coupled to an output node 44; a first low side transistor 20 coupled to the output node 44; a second low side transistor 24 coupled in parallel with the first low side transistor 20; a coupling transistor 23 coupled between the output node 44 and a control node of the second low side transistor 24; a transmission gate 50 coupled between a control node of the first low side transistor 20 and a control node of the coupling transistor 23; and feedback circuitry 58 coupled between the output node 44 and the transmission gate 50 for controlling the transmission gate 50.

Abstract: A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”.

Abstract: An improved memory cell (600) for use in a high-intensity light environment. The memory (600) comprises a substrate (616) capable of generating photocarriers when exposed to radiant energy, at least one transistor (602), at least one capacitor (604), and address node (610) electrically connecting the transistor (602) and the capacitor (604), and an active collector region (626). The active collector region (626) is fabricated in the substrate (616) in a position to allow the active collector region (626) to recombine photocarriers traveling through the substrate (616) thus preventing the photocarriers from reaching the address node (610).

Abstract: The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the second dielectric layer. Next, the first, second, and third dielectric layers are patterned to form a contact hole therein. A doped polysilicon layer is then formed within the contact hole and over the third dielectric layer, followed by the formation of a fourth dielectric layer over the doped polysilicon layer. A patterning step patterns the fourth dielectric layer and the doped polysilicon layer to define a storage node. A hemispherical grained silicon layer is then formed on the fourth dielectric layer, on sidewalls of the storage node, and on the third dielectric layer.

Abstract: The invention is a semiconductor package (10) and to the method of making in which the backside (23) of a semiconductor die (13) is mounted to one part of a package (11) with an adhesive (12) which may be both thermally and electrically conductive. The face (22) of the semiconductor die (13) is attached to a second part of the package (18) to direct heat away form the face (22) of the semiconductor die (13).

Abstract: The image sensing device includes an image sensing area 22 having an antiblooming drain structure; and a frame memory area 24 coupled to the image sensing area 22 for storing charge from the image sensing area, wherein during charge integration, the antiblooming drain is biased at a first level, and during charge transfer to memory, the antiblooming drain is biased at a second level such that the image sensing area 22 will have a higher charge capacity than during the charge integration.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: An integrated circuit (SAI0) comprises a first SOI transistor (T4) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. The integrated circuit further includes a second SOI transistor (T5) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. In the integrated circuit, one of the plurality of nodes of the first SOI transistor is connected to receive a first differential input signal.

Abstract: The invention comprises a differential sample-and-hold circuit including a differential gain stage. The differential gain stage comprises a control transistor and an output node. The differential gain stage further comprises a primary load coupled between the control transistor and the output node. A hold control circuit is coupled to the base of the control transistor, the hold control circuit operable to effect a reduction of the base voltage of the control transistor and a corresponding reduction of the voltage at the output node of the differential gain stage.

Abstract: The application discloses a new digital IIR filter structure which uses at least one fewer multiplier than presently available in current digital IIR filter structures. In particular, by constraining one or both endpoint values (0 and fs/2) to unity, the disclosed approach uses 2 multiply operations instead of 3 for first-order structures and 3 multiply operations instead of 4 or 5 for second-order structures. This multiplier reduction enhances the capacity of the current audio equalizer digital signal processor by 30%.

Abstract: A programmable logic device (130) as may be used in a communication system device such as a digital subscriber line modem (408) to perform Reed-Solomon decoding upon a received frame of digital values is disclosed. The programmable logic device (130) may be implemented as a DSP (130) or a general purpose microprocessor, for example. According to one disclosed embodiment of the invention, a group of look-up tables (60) are arranged, each look-up table (60) associated with one of the possible power values of a finite field, number up to twice the number of correctable errors. The contents of each entry (SYN) of the look-up tables (60) correspond to the finite field (e.g., Galois field) multiplication of a primitive element raised to an index power with a character of the finite field alphabet. Galois field multiplications (62) in syndrome accumulation may now be performed with a single table look-up operation.