Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). A second disposable gate structure (28) of the second, complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A capping layer (60) may be formed over the first and second regions (16, 18) including the first and second disposable gate structures (26, 28). A portion (62, 64) of the first and second disposable gate structures (26, 28) may be exposed through the capping layer (60). A second disposable gate cap (66) may be formed over the exposed portion (64) of the second disposable gate structure (28) and at least part of the first disposable gate structure (26) removed.

Abstract: A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

Abstract: A wafer of semiconductor material has plural dies formed on the wafer with scribe-line areas of semiconductor material around the each die. Each die includes functional circuitry having input and output bond pads and the dies are arranged adjacent one another in a regular array. Each die includes selectable internal connecting leads connecting the input and output bond pads along one side of the die and the input and output bond pads along an opposite side of the die. External connecting leads are formed on the wafer in the scribe-line areas. The external connecting leads connect input and output bond pads of one die and input and output bond pads of an adjacent die. There is one external lead connecting one bond pad on one die with one corresponding bond pad on the adjacent die.

Abstract: A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of at least one of the isolation regions to expose a first area of the substrate, depositing a mask layer over the integrated circuit including the first area, forming the mask layer to expose a second area of the substrate within the first area, converting a portion of the substrate to a selectively etchable material, where the selectively etchable material lies in an area subjacent to the second area and extends only partially to the bottom surface of the substrate, selectively etching the selectively etchable material to form a void, removing the mask layer to expose the isolation region, depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region, depositing a dielectric layer over the conductive layer extending at least to the height of the isolation region, polishing the surface of the d

Abstract: A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N+ control gate (26). N+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

Abstract: An acoustic noise suppression filter including attenuation filtering with a noise-free estimate based on a codebook of line spectral frequencies.

Abstract: A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: An FET and DRAM using a plurality of such FETs wherein each transistor has a body region (27) of a first conductivity type including a relatively high VT region (p) and a relatively low VT region (p−), the high VT region disposed contiguous with the low VT region. A pair of source/drain regions (23, 25) of opposite conductivity type are disposed on a pair of opposing sides of the low VT region. The transistor includes a gate oxide (31) over the body region and a gate electrode (29) over the gate oxide and spaced from the body region. The body region is p-doped or n-doped with the high VT region more heavily doped than the remainder of the body. In a further embodiment, the FET includes a body region of a first conductivity type which includes a relatively low VT region and a first pair of relatively high VT regions on a first pair of opposing sides of the body. A pair of source/drain regions of opposite conductivity type are disposed on a second pair of opposing sides of each of the low VT region.

Abstract: A programmable interrupt controller (510) for a single interrupt architecture processor (518) includes a plurality of interrupt sources (502) each operable to generate an interrupt. A dynamically alterable interrupt mask (508) selectively blocks interrupt signals for the interrupt sources (502). Interrupts permitted by the dynamically alterable interrupt mask (508) are processed by an interrupt handler (500) for the single interrupt architecture processor (518) in order of priority. In addition, processing for a lower priority interrupt is interrupted in order to process a later received higher priority interrupt permitted by the dynamically alterable interrupt mask (508).

Abstract: Fabrication of metal-on-conductive-diffusion-barrier-on-gate-dielectric structures is done by: etching the metal, by plasma-assisted anisotropic etching, down to and into the barrier metal; and then etching the remainder of the barrier layer by a dry chemical-downstream-etching process, during which the barrier layer is not exposed to ion bombardment. In the case of tungsten over titanium nitride, high selectivity and good profiles are preferably obtained, by: during the tungsten etch, using a combination of low temperature, relatively low bias, and the addition of nitrogen; and during the titanium nitride etch, using a chemical downstream etch instead of the conventional wet etch (in boiling H2SO4). (This allows better control of undercutting, and eliminates wet strip process.

Abstract: A method is disclosed of nitridating an oxide containing surface the disclosed method includes the steps of, obtaining a substrate, growing an oxide layer on the substrate, exposing the surface of the oxide layer to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer on the oxide layer resistant to chemistries used to etch oxide.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: The use of silicon carbide to form sidewall spacers allows the use of a lower temperature deposition step, and provides greater etch selectivity with respect to oxide.

Abstract: A Class-D switching amplifier (30, 40) having a ternary mode of operation. Signal processing (21, 22) is provided to eliminate the potential of crosstalk within one channel by introducing a time delay into the system. A susceptible crosstalk point is moved away from a zero-crossing point to a higher power level, which is advantageous in low-end audio applications. A time delay is introduced to one ramp signal (RAMPB) in the first implementation (30), and an in-sync generator (42) is utilized in another implementation (40) using offset switching in the comparitors (40, 42) to create the time delay (&Dgr;t).

Abstract: A data model for an information repository (10) models data as objects (12), the relationships (14) or interdependencies between the data, their physical storage or access information (18) and rules or methods of accessing the data (16).

Abstract: Segmentation of FLASH Memory arrays allows the global and local bit lines to be isolated, greatly reducing global bit line capacitance, reducing bit line stress, and eliminating boot block disturb effects. Reduction in bit line capacitance also results in fast access time greatly improving the ability to implement larger arrays without paying severe access time penalties.

Abstract: A low noise, low current, high bandwidth differential amplifier circuit (30), including a first amplifier (44) driving a first transistor X1 and having a first current source I2 coupled to an input of the first amplifier (44). A first feedback resistor R3 is coupled between the first current source I2 and the first transistor X1, and a second resistor R4 is coupled to the first resistor R3. A second amplifier (46) drives a second transistor X2, and has a second current source I3 coupled to an input of the second amplifier 46. A third feedback resistor R5 is coupled between the second current source I3 and the second transistor X2. A fourth resistor R6 is coupled to the third resistor R5. The first R3 and third R5 feedback resistors are driven by the first I2 and second I3 current sources rather than by the first (44) and second (46) amplifiers, respectively, allowing the first and second amplifiers (44, 46) to be single stage amplifiers.

Abstract: A method of preparing a surface for and forming a thin film on a single-crystal silicon substrate is disclosed. One embodiment of his method comprises forming an oxidized silicon layer (which may be a native oxide) on at least one region of the substrate, and thermally annealing the substrate in a vacuum while supplying a silicon-containing flux to the oxide surface, thus removing the oxidized silicon layer. Preferably, the thin film is formed immediately after removal of the oxidized silicon layer. The silicon-containing flux is preferably insufficient to deposit a silicon-containing layer on top of the oxidized silicon layer, and yet sufficient to substantially inhibit an SiO-forming reaction between the silicon substrate and the oxidized silicon layer. The method of the invention allows for growth or deposition of films which have exceptionally smooth interfaces (less than 0.1 nm rms roughness) with the underlying silicon substrate at temperatures less than 800° C.

Abstract: A class AB amplifier (400) is disclosed, having a first input node (402), a second input node (404), and an output node (406). A push-pull input stage (412) includes cross-coupled pairs of transistors, which form a charge current path and a discharge current path. When the voltage at the first input node (402) is greater than the voltage at the second input node (406), the amount of current drawn in the charge current path increases, and the amount of current drawn in the discharge current path decreases. When the voltage at the first input node (402) is less than the voltage at the second input node (404), the amount of current in the charge current path decreases while the amount of current in the discharge path increases. A first and fourth current mirror (422 and 428) are coupled to the charge current path, and a second and third current mirror (424 and 426) are coupled to the discharge current path.

Abstract: A voltage translator circuit for driving the rows or wordlines of Flash EEPROM memories, having control logic voltages in the range 0 to 3.3 volts, as well as operating voltages needed for reading, programming or erasing operations in the range −9 to 12 volts. The voltage translator circuit includes a first feedback transistor (TP4), the gate of which (node 18) is directly driven by the wordline, and a second feedback transistor (TN5), the gate of which is also driven by the wordline (node 18), inserted between the connection node (node 6) between the first feedback transistor (TP4) and the gate region of a first switch transistor (pull-up 3) and the input node (node 0) on the gate region of a second switch transistor (pull-down 2).