Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: An integrated circuit (10) includes a P-epi substrate (12) having therein an n-well isolation layer (13) and a p-well (14) within the n-well. The p-well includes adjacent an upper surface thereof a p+ layer (18) having several elongate parallel openings (21-23) therethrough. Each of the openings has therein a respective n− RESURF layer (26-28). Each n− RESURF layer has therethrough a respective further elongate opening (31-33), and has a uniform horizontal thickness all around that opening. Each of the openings in the RESURF layers has therein an n+ finger (36-38). The p+ layer and the n+ fingers each have a vertical thickness which is greater than the vertical thickness of the n− RESURF layers. The p+ layer serves as the anode of a zener diode, and the n+ fingers are interconnected and serve as the cathode.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: A capacitive fluid pressure sensor (10, 10′, 10″) particularly adapted for use with fluids which are incompatible with conventional elastomeric fluid seals is shown in which a thin, relatively flexible metal diaphragm (18, 18′, 18″) is disposed over a fluid pressure receiving recess (16d, 16d′) formed in a bottom wall of a hexport housing (16, 16′) and hermetically attached thereto. A capacitive sensor element (12) having a pressure sensitive surface (12b) is disposed in the housing with the pressure sensitive surface placed against the metal diaphragm with a plastic intermediate layer (20, 20′, 20″, 20′″) disposed between the metal diaphragm and the sensor element to minimize hysteresis and output error. The metal diaphragm and plastic layers are shown to be flat members in certain embodiments (18, 18′ and 20, 20″) and corrugated in another embodiment (18″, 20″).

Abstract: A circuit is designed with a delay circuit (300,301,500) coupled to receive a bias (256) and a reference signal (242). The delay circuit produces a series of phase signals (214). The phase signals are spaced apart in time in response to the bias. Each phase signal has a respective time after the reference signal. Each phase corresponds to logic states of a plurality of data signals. An encoder circuit (900,1100) is coupled to receive a first phase signal and a first plurality of data signals (212). The encoder circuit produces a first encoded data signal (220) at a time corresponding to the respective time of the first phase signal. A decoder circuit (600,800) is coupled to receive a second phase signal and a second encoded data signal (220) corresponding to the respective time of the second phase signal. The decoder circuit produces a second plurality of data signals (212) corresponding to the second phase signal.

Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: A tone display method is provided that can prevent image quality deterioration of the dynamic image and can avoid a cost increase. When an image with 256 tones is displayed, one field is divided into 37 subfields for one color. Among the 8 bits corresponding to the 256 tones, the six high-order bits from the third bit are displayed by means of time width modulation using 35 subfields SF3-SF37 having weights of ““4” and “8”. The two low-order bits are displayed on a binary base using two subfields SF1 and SF2 whose weights are “'1” and “2”, respectively.

Abstract: Ferroelectric memory with one-capacitor/one-transistor cells and a reference cell with double the capacitance plus a sense amplifier for comparing transient currents in resistors at the sense amplifier inputs. The reference cell includes a diode to prevent reference capacitor polarization switching.

Abstract: An organic light emitting diode with dielectric barriers (120, 106) at both the anode-organic and the cathode-organic interfaces.

Abstract: In code division multiple access (CDMA) cellular-based communication systems in which a user station can demodulate multiple signals, not necessarily coming from the same base station, a method to rapidly identify at the user station spread spectrum code offsets at which actual signal paths exist. In such a system a plurality of base stations transmit data unmodulated pilot signals, wherein each of the pilot signals comprises a radio frequency signal modulated by a predetermined spread spectrum code at a predetermined rate. The base stations modulate their respective radio frequency signals with the same spread spectrum code but each of the base stations have a different, predetermined offset of the spread spectrum code from other of the base stations in a given vicinity, or, alternatively, the base stations modulate their respective radio frequency signals with different spread spectrum codes that are known by the user station.

Abstract: According to one embodiment of the invention, a method of buffering instructions in a processor having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and writing the fetch instruction into an instruction buffer after the decode stage is no longer stalled.

Abstract: The inventive apparatus includes a first filter which receives an analog-based input signal and a feedback signal, performs equalization on the analog-based input signal and the feedback signal, and outputs an equalized signal based on the analog-based input signal and the feedback signal. The first filter may include an analog finite impulse response filter. The apparatus also includes an analog to digital converter which receives the equalized signal and outputs a digital signal converted from the equalized signal in accordance with the feedback signal. In addition, the apparatus includes a phase detector which receives the digital signal, detects a phase difference therefrom and outputs a signal corresponding to a magnitude of the phase difference. The apparatus also includes a second filter and a voltage controlled oscillator.

Abstract: The sidewall nitride etch is modified to leave a thin layer of nitride covering the silicon in a DRAM array. The nitride layer prevents damage to the silicon and improves the integrity and refresh time of the array.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A method and system of measuring misalignment between two levels wherein there is provided a first grating pattern (19, 21, 23, 25, 3, 5, 7, 9) on a first layer (1) and a second grating pattern (19′, 21′, 23′, 25′, 3′, 5′, 7′, 9′) on a second layer (41) capable of providing Moire fringes when disposed over the first grating pattern and which is disposed over the first grating pattern whereby the first and second grating patterns are capable of providing Moire fringes. Misalignment of the first layer relative to the second layer is measured from the position of the Moire fringe provided by the first and second grating patterns either visually or by optical instrumentation. The second layer is preferably transparent.

Abstract: A programmable fast packet switch testbed (10) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The programmable switch (10) is arranged as an add-on peripheral to a conventional computer system including a host central processing unit (CPU) (2). The switch (10) includes a plurality of port processors (14) in communication with port interfaces (12); each of the port interfaces (12) is a conventional interface for high data rate communication, while the port processors (14) are programmable logic devices. The switch fabric is realized in a multiple slice fashion, by multiple programmable logic devices (18). A central arbiter (30), also realized in programmable logic, controls routing of cells within the switch (10).

Abstract: A microphone bias amplifier circuit (30) and method for biasing a microphone with an amplifier circuit. The amplifier circuit (30) has an input stage (34) coupled to an output stage (40). The output stage (40) includes a first transistor (M1) coupled to a feedback loop (32) provides a variable source current (13) to the first transistor (M1) and the output stage output Vout. The feedback loop (32) includes an amplifier (36) coupled to the first transistor (M1) and a first current source (I2) conducted through a second transistor (M2) and coupled to the amplifier (36). The amplifier (36) controllably drives a third transistor (M3) coupled to a voltage source (AVDD) to generate the variable current source (I2). The gates of the first (M1) and second (M2) transistors are coupled together and driven by the input stage (34).

Abstract: The improved rinse tank includes an external shell and an internal shell. For one embodiment, the external shell preferably defines a five sided open-top tank with a top open to the atmosphere. The internal shell is preferably disposed within the external shell and has a configuration that will accommodate at least two semiconductor wafer boats filled with six inch semiconductor wafers. The external shell is preferably sized large enough to completely immerse the wafer boat and wafers in water when the rinse tank is filled. A chamber may be formed between the external shell and the internal shell within the lower portion of the rinse tank. Two or more deionized water inlets may be provided at the bottom of the rinse tank at opposite corners. Three or more compressed air nozzles may also be provided at the lower portion of the rinse tank. Multiple deionized water jet ports are provided at the internal shell.

Abstract: A wire bonding method includes aligning the face of a capillary along a first direction to make a first wire bond at a first bond point. The capillary face is realigned to a second direction to make a second wire bond at a second bond point. The realignment may be achieved by a system including an wire bonding capillary having an indicator located thereon. A detector detects a signal from the indicator. The signal corresponds to a rotational alignment of the capillary and, therefore, to a direction of alignment of the capillary face. A first signal indicates a first alignment of the capillary face and a second signal indicates a second alignment of the capillary face. The signals may each have a relative signal strength which indicates rotational an offset of the capillary face from a given direction.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.