Abstract: An ultra low voltage CMOS, class AB power amplifier has internal compensation using only parasitic gate capacitance.

Abstract: A method of selecting a set of color sources for an image display system, the image display system creating a color image from at least three single-color color sources. According to one embodiment of the present invention, the method comprises selecting a first, second, and third color source. The first and second color sources are divided into a high-efficiency group and a low-efficiency group based on the efficiency of the color source. If the first color source is selected from the high-efficiency group (1102), the second color source may be selected from either the high-efficiency group or the low-efficiency group (1104). If the first color source is selected from the low efficiency group (1102), the second color source is selected from the high-efficiency group (1106). According to one embodiment of the present invention, the third color source is selected (1108) without first sorting the third color sources into high and low-efficiency groups.

Abstract: A circuit (10) and method for dibit detection in a mass data storage device includes concurrently operating magnitude (16), polarity (18), and peak value (20) qualification circuits. The magnitude qualification circuit (16) produces a magnitude qualification output signal when a magnitude of the read back signal exceeds a predetermined magnitude threshold. The polarity qualification circuit produces a polarity qualification output signal when a polarity of the read back signal is of a predetermined polarity. The peak value qualification circuit produces a peak value qualification output signal at a time at which a peak value of the read back signal occurs during a predetermined period. When the magnitude qualification output signal, the polarity qualification output signal, and the peak value qualification output signals simultaneously occur, a dibit detection signal (118) is produced.

Abstract: A circuit (14) for aiding proper frequency lock in a phase locked loop (12) includes a phase detector (40) adapted for receiving an input signal and an oscillator output signal from the phase locked loop (12) and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip detector (42a) receives the up pulse width modulated cycle slip signal and generates an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal. A down cycle slip detector (42b) receives the down pulse width modulated cycle slip signal and generates a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal. A phase correction circuit (41, 43) is provided for generating a steering signal in response to the up and down cycle slip signals.

Abstract: A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate.

Abstract: A mobile device charging cradle (46) to enable short distance wireless communication between a personal computer (10) and at least one other short distance wireless communication enabled electronic device (50). In a preferred embodiment of the invention, a short distance wireless radio (transceiver—Bluetooth enabled) (44) and antenna (42) are added to a charging cradle to produce a combination charging and short distance wireless communication enabled cradle (46) which is coupled via a data cable (12) to a personal computer (10). The short distance wireless (in this case RF) communication enabled cradle enables a system in which a legacy architecture personal computer may communicate with other short distance RF communication enabled electronic devices. Such communication is enabled whether or not another RF communication enabled portable electronic device is coupled to the cradle.

Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10−4 to about 10−7 until the silicon oxide layer has reached a predetermined thickness.

Abstract: In a procedure for the digital evaluation of the analogue output signals from a resolver with at least two stator windings, arranged perpendicular to each other on a stator, and at least one rotor winding on a rotor able to rotate in relation to the stator, a sinusoidal signal is applied to the rotor winding and sine, respectively cosine shaped signals, depending on the angular position of the stator in relation to the rotor, are extracted from the stator windings. These signals are further processed after conversion into digital signals by application of the inverse tangential function, in order to compute an angular value for the relative angular position between the rotor and the stator. This angular value is affected by a propagation delay time error, which is compensated for by the introduction of a control loop.

Abstract: Distributed buffering memory device (10) is provided which includes memory circuitry (12) located therein and independent buffering circuitry (16). Device (10) can be used in an array of devices where buffering circuitry (16) is employed to buffer the signals necessary for the array. Each independent buffer is employed to buffer a signal and supply that signal to a bank unique input bus which is used to drive the inputs of the array.

Abstract: A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

Abstract: A display system using red, green, blue, and white light. The system derives data for the white portion of a color wheel or a white device from the red, green and blue data. The white portion of the color wheel is controlled as if it were another primary color on the wheel. Errors are prevented by a correction applied if the unfiltered light from the source has a different color temperature than the white light produced using the red, green and blue segments of the color wheel, or the devices for those colors. Analysis is performed on the data to determine if white light is necessary to be added to each frame of data.

Abstract: A video decoder having an input buffer for receiving an encoded and compressed data stream, parsing circuitry for removing header information from said data stream, circuitry for decoding said data stream, circuitry for decompressing said data stream, circuitry for selecting predetermined portions of preselected frames, memory for storing said decompressed data stream and selected portions of said preselected frames, and circuitry for reconstructing selected portions of said preselected frames is provided.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: The invention provides methods and systems for power control in point-to-multipoint communications systems. Methods are described for downstream using an off-the-air monitor 31 and pick-up antenna 33. The monitor detects the power level of the pick-up signal and a control signal sets the transmittal output from the base station in proportion to the detected composite power level.

Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer (layer 434 of FIGS. 1b-1d) on the upper surface of the patterned dielectric layer and on the bottom and the sidewalls of the opening in the patterned dielectric layer; forming a conductive layer (layer 436 of FIGS.

Abstract: A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (107) over the high-k dielectric (107). A conductive layer (110) is formed over the nitride layer (107) forming the gate electrode.

Abstract: A trellis shaping method is described that may be used for suppressing DC components and/or Nyquist frequency components from the outputs of a PCM (56K) modem. The technique is based on convolutional codes. The code is generated through the use of a Viterbi decoder. Data bits are mapped for transmission into a set of n magnitudes and (n−k) sign bits s. The sign bits s are passed through (HT)−1 to get preliminary sing bits t=s (HT)−1 of size n. (HT)−1 is a matrix of size (n−k) by n which represents the left inverse of the syndrome-former matrix HT of convolutional code c=b G, defined so that G HT=0. The convolutional code is then added to sign bits t through an XOR operation to give final sign bits s (HT)−1+b G. After transmission, the final sign bits are passed through HT to give an output of (s (HT)−1+b G) (HT))=s, for recovery of the data bits.

Abstract: PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.

Abstract: A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC13 Bn13 ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory.

Abstract: An improved method of providing a pitch shifted or frequency transformed signal includes frequency scaling the original signal (12) and generating a desired spectrum envelope of the frequency transformed signal, As(z) by LPC analysis of the original signal (11). Further the method includes producing an approximation of the spectrum envelope of the frequency scaled signal As(z, &bgr;) by performing LPC analysis on the original signal (11), obtaining LSFs (13), scaling (15) and transforming the scaled LSFs back to LPC (17).