Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.

Abstract: One anode 350 and multiple cathodes 50, 60, 70, and 80 create a large display field emission device. The use of one anode 350 facilitates an image which is seamless to the viewer. The use of multiple cathodes 50, 60, 70, and 80 allows a single image or multiple images to be displayed. The use of multiple cathodes also provides fast refresh rates and a high resolution image. Methods of fabricating and operating the large display field emission device are disclosed.

Abstract: An improved method of providing a pitch shifted or frequency transformed signal includes frequency scaling the original signal (12) and generating a desired spectrum envelope of the frequency transformed signal, As(z) by LPC analysis of the original signal (11). Further the method includes producing an approximation of the spectrum envelope of the frequency scaled signal As(z, &bgr;) by performing LPC analysis on the original signal (11), obtaining LSFs (13), scaling (15) and transforming the scaled LSFs back to LPC (17).

Abstract: An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step 102 of FIG. 1); forming a layer of the metallic conductor on the dielectric layer (step 104 of FIG. 1); removing a portion of the layer of the metallic conductor on the dielectric layer (step 106 of FIG. 1); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step 110 of FIG. 1). Preferably, the plasma contains a substance selected from the group consisting of: NH3, N2H2, H2S, and CH4, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof.

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

Abstract: A pulse driven two lamp (40, 50) single light valve (62) imaging display system (10). The first lamp (40) is used to generate red light, and the second lamp (50) is used to generate blue and green light. A beam splitter (46) combines the white light of the two light sources, and directs the light to a color wheel (26). The first red lamp (40) is driven at a peak power being 3X the average power rating of the lamp for ⅓ of a video frame. The second blue-green lamp (50) is pulse driven at a peak power being 150% its average power rating for ⅔ of a video frame. The present invention achieves improved color balance and increased intensity, and is a simple and cost effective architecture.

Abstract: A method for designing and fabricating an integrated circuit is described. An increase or a decrease in a total propagation delay time 311 of a signal on a victim net 203 is accurately modeled using a modified decoupled simulation model 300. Victim net 203 is modeled as a distributed capacitor 320a-c that has a total value equal to Cgnd+2*K*Ccoup. A match propagation delay time which includes a variation in propagation delay caused by signal coupling from aggressor nets located adjacent to the victim net is determined by simulating a representative circuit using a coupled distributed load simulation model to accurately determine the match propagation delay time. K is determined using an equation in which K=1+(match delay−unmodified delay)/(2*R*Ccoup). R is the effective drive resistance of a buffer which drives the victim net and associated signal trace resistance.

Abstract: A method and circuit for operating a polyphase dc motor in which discontinuous sinusoidal drive voltages are applied to the windings of the motor in predetermined phases. The discontinuous portion of the sinusoid is timed with the bemf zero crossings. Bemf zero crossings are detected, and phases of the drive voltages are adjusted to have zero crossings substantially in the discontinuities of the drive voltages. The method and circuit result in motor operation with significantly reduced acoustic motor noise.

Abstract: The invention relates to the interfacing of high speed, low voltage data streams with CMOS circuits and, more specifically, to converting low voltage, differential ECL signals levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability. This is accomplished by making first stage inverters 5 and 6 as geometrically small as possible subject to the design rules in use to minimize the capacitance at the input of these inverters. The inputs of the first stage inverters are clamped by bias circuits 9/10/11 and 12/13/14 at DC levels so as to provide a narrow range of operation. Additional output inverters 7 and 8 act as buffers to provide the needed capacitive load drive capability.

Abstract: A system (10) for coupling conductive pellets (40) to a component (12) of an integrated circuit has a substantially planar ribbon (14) that includes a conductive material. A punching apparatus (16) and (38) penetrates the ribbon (14) to form the conductive pellets (40). The punching apparatus (16) and (38) also moves relative to the component (12) to the conductive pellets (40) to the component (12).

Abstract: A switched-capacitor circuit (35), and analog-to-digital converter (50) incorporating the same, is disclosed. The disclosed switched-capacitor circuit (35) receives differential input signal voltages (Vin+, Vin−), and differential reference voltages (Vrefp, Vrefn), based upon which differential output voltages (Vout+, Vout−) are generated by way of sample-and-hold, and amplify, operations. In a larger context, such as in a pipelined ADC (50), multiple switched-capacitor circuits (35) are implemented, each receiving the differential reference voltages (Vrefp, Vrefn) from a voltage reference circuit (20).

Abstract: An optical system for illumination spatial light modulators. The optical system includes a tall color splitting prism (16) with substantially symmetrical face bonding areas, thereby eliminating the need for external holding plates. The face bonding areas (62) are outside the optically active area. The tall prism (16) allows for better control of stray light, including a heat sink (41) for absorbing stray or OFF state light, preventing overheating of the optical assembly. The tall prism (16) also allows adjustments to be made to any other optical components such as projection lenses and TIR prisms (14).

Abstract: An operating system preferably for use with a digital signal processing target is disclosed which minimizes time and space requirements on the target DSP chip. The operating system is also configured in accordance with parameters entered by a user regarding the application being developed.

Abstract: A potentiometric digital to analog converter includes switches to electrically connect a string of n resistors between two voltage supplies to charge a first capacitor (C1) through a first tap and store the charge and then to reverse the electrical connections of the string to the two power supplies to charge a second capacitor (C2) through a second tap connected at an inverse location symmetrical about the average voltage of the voltages at the supply connectivity switches and store the charge of the second capacitor. The voltage (VA, VB) on the two capacitors is then averaged to provide a ratiometric output voltage which is insensitive to the drift of values of the string of resistors.

Abstract: The objective of the invention is to provide a type of semiconductor memory device whose antifuse can be formed without any additional film manufacturing process. A first electrode is formed by a first polysilicon film 37 formed on semiconductor substrate 30 and a second polysilicon film 39 deposited on the surface of the first polysilicon film. The first electrode, a dielectric film formed on the surface of the first electrode, and a second electrode form capacitor 11 in the memory cell. An antifuse 12 with the same configuration as capacitor 11 is formed in the semiconductor memory device. Because there is no need to use an additional film, the manufacturing cost is low, and antifuse 12 can be easily arranged. It is also possible to form antifuse 13 by forming instead of depositing the second polysilicon film 39 on the surface of the first polysilicon film 39.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: An isolation circuit (10) and method for providing dc isolation between two integrated circuit devices (11) and (12) that may be referenced to different ground potentials is presented. The isolation circuit (10) includes, in each circuit, an output buffer (20, 20′) connected to deliver a signal to an input/output pin (16, 17) of the circuit (11, 12) with which the output buffer is associated. A capacitance (30), which may be a single capacitor or a combination of capacitors, is connected to the pins (16, 17) of each of the circuits (11, 12), and in each circuit (11, 12), an input buffer (22, 22′) is connected to receive a signal delivered onto the I/O pin (16, 17). The input buffer (22, 22′) includes a circuit for resisting a charge leakage from the capacitor, which, preferably is a bus holder circuit (36), or the like. In another embodiment, a transformer (85) is used to provide dc isolation between the two integrated circuits (62, 64).

Abstract: A compact data line arrangement (600) includes “twisted” data line pairs (604a-604c) disposed in a first direction. Each twisted data line pair (604a-604c) includes an upper segment pair (608a-608f) that is connected to a lower segment pair (610a-610f) by a twist structure (612a-612c). The upper and lower segment pairs (608a-608f and 610a-610f) can be formed with a first pitch using phase-shifted lithography. The twist structures (612a-612c) are formed from a second conductive layer, and have a greater pitch than the first pitch. The twist structures (612a-612c) are generally arranged in a second direction that is perpendicular to the first direction. Selected twist structures (612b) are offset in the first direction with respect to adjacent twist structures (612a and 612c). The offset twist structures (612a-612c) allow supplemental conductive lines (618) to be formed from the first conductive layer that extend in the first direction, between adjacent offset twist structures (612a and 612b).

Abstract: A CMOS area array sensor with reduced fixed pattern noise. Device threshold voltage variations are minimied using a Sequential Correlated Double Sampling technique in a column circuitry.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.