Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A monolithic power amplifier system is described which comprises a biasing system 50, transconductance amplifier circuit 42 and a transimpedance amplifier circuit 44 biasing network 50 is operable to generate a bias voltage which is used by the transimpedance amplifier 44. The transimpedance amplifier 44 receives an input current signal from the transconductance amplifier 42. The changes in the input current are communicated to a pull-up transistor 184 and a pull-down transistor 190 which drive an output voltage VOUT at sufficient levels to power the cathode of an electron gun of a video system.

Abstract: The conductivity of gate structures can be improved by siliciding the entire gate. Additionally, silicon sidewalls can be added to the gate after the “smiling” oxidation, but before silicidation, which provides a new tool for drain profile engineering.

Abstract: A head-disk assembly 200 is directly connected to a host computer by arm 120 and arm 130. A housing connector 100 which includes the arms 120 and 130 is directly connected to the host computer to provide physical support for the head-disk assembly. Electrical connection to the host computer is through an electrical connector 300 of a printed circuit board 400. Consequently, there is no need for a large printed circuit board.

Abstract: A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Abstract: A method and apparatus (10) for breaking a wafer (24) into die (26) having a high aspect ratio. In one embodiment, a multi-radii dome (12) is utilized to controllably break the wafer in two directions. The two different dome curvatures (R1, R2) provide an even, controlled, force along the kerfs in both the X-direction and the Y-direction. In another embodiment, a cylindrical dome (80) being curved (R3) in the Y-direction and flat in the X-direction is used to break a wafer into die having exceptionally high aspect ratios. The present invention reduces the likelihood of die fracture in the long dimension during the wafer break process. The wafer (24) is mounted on stretchable wafer tape (18) during the break process to prevent the die edges from contacting and rubbing with one another after the break process. The present invention allows separation of die of exceptionally large aspect ratios such as those having a 1:25 aspect ratio.

Abstract: An MPEG video playback method and system that reduces delay at the time of video reproduction of an MPEG-compressed video signal. The invention discloses a video reproduction method in a video reproduction system containing an error-correction means, an MPEG decoding means, and buffers. In one embodiment, the signal held in the buffer is output as the video playback signal (block 6), and the output from the MPEG decoding means is output as a video playback signal (block 5). An embodiment of a method and system in which the buffer is arranged upstream to the MPEG decoding means is also disclosed.

Abstract: A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic perovskite material (5) is formed over the silicon substrate and substantially matched to the lattice constant of the silicon substrate. A layer of crystallographic silicon (7) is formed over the perovskite layer substantially matched to the lattice constant of the perovskite layer. The perovskite layer is formed by the steps of placing the silicon substrate in a chamber and then evaporating a layer of barium strontium oxide (3) thereon with a thickness of from about three to about six Angstroms and then evaporating a layer of calcium strontium titanate (5) thereon having a thickness of from about six to about 25 Angstroms thereon in the case of a tunneling diode.

Abstract: A rail-to-rail input stage (20) for an operational amplifier having a constant transconductance (Gm) over a common mode range. The input stage has a cross-coupled quad circuit (Q9, Q10, Q15, Q16) having an essentially infinite transconductance, and pair of transistors (Q5, 6) running at the same current as input transistors (Q1, Q2) when active, whereby the pair of transistors (Q5, Q6) establish a constant transconductance of the input stage (20).

Abstract: Protection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14).

Abstract: A dynamic logic circuit (16) operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a precharge node (18PN) coupled to be precharged to a precharge voltage (VDD) during the precharge phase and operable to be discharged during the evaluate phase. The dynamic logic circuit further comprises a conditional series discharge path connected to the precharge node and comprising a plurality of transistors (18L, 18DT, 20SDVN) operable to conditionally couple the precharge node to a voltage different than the precharge voltage. Further, the dynamic logic circuit comprises an output inverter (18INV) having an input connected to the precharge node and comprising a plurality of transistors (18INVP, 18INVN) for providing an output signal representative of a voltage at the precharge node during the evaluate phase.

Abstract: An optical coating for an uncooled focal plane array detector where the optical coating comprises a porous film. The porous film preferably comprises a xerogel.

Abstract: An analog-to-digital converter (“ADC”, 40) comprising an input (VIN2) for receiving an input analog voltage. The ADC further comprises a digital-to-analog circuit, comprising a meandering string (12′) of series connected resistive elements (R0′-R14′) having a plurality of voltage taps (T0′-T15′), as well as a number of bit lines (BL0′-BL3′) and a number of word lines (WL0′-WL3′). For a given input analog voltage, the given input analog voltage is closest to a voltage at a selected one of the plurality of taps. In addition, the selected one of the plurality of taps is associated with one of the number of bit lines and one of the number of word lines. Additionally, the ADC further comprises a flash circuit (44, 46, 48, 50, 42, CAT0′-CAT3′) coupled to receive the input analog voltage from the input and in response to identify either the one of the number of bit lines or the one of the number of word lines.

Abstract: A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of the raised source/drain region is doped n-type. P-type dopants from first layer (106a) are diffused into the substrate to form a pocket barrier region (105). N-type dopants from second layer (106b) diffuse into first layer (106a) so that it becomes n-type and into the substrate to form source/drain junction regions (104). P-type pocket barrier region (105) thus provides a barrier between the source/drain junction regions (104) and the channel region (108).

Abstract: A palladium plated lead frame (34) for integrated circuit devices has a nickel strike (36) and a palladium/nickel alloy layer (38) separating the copper base metal (28) from the nickel intermediate layer (40) in order to prevent a galvanic potential from drawing copper ions from the base metal layer (28) to the top layer (42). The nickel strike (36) and palladium/nickel alloy layer (38) also reduce the number of paths through which a copper ion could migrate to the top surface resulting in corrosion.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: Method and system of interconnecting conductive elements includes forming a lower conductive element (14) having a lower contact section (22) with a width (24) not more than substantially that of an adjacent section (26) of the lower conductive element (14). A first insulation layer (18) may be formed outwardly of the lower conductive element (14). An upper conductive element (16) may be formed outwardly of the first insulation layer (18). The upper conductive element (16) may have a upper contact section (28) with a width (30) not more than substantially that of an adjacent section (32) of the upper conductive element (16). A second insulation layer (20) may be formed outwardly of the first insulation layer (18) and the upper conductive element (16). A contact hold (40) may be formed in the first and second insulation layers (18, 20) exposing a lower contact area (42) of the lower contact section (22) and an upper contact area (44) of the upper contact section (28).

Abstract: This invention pertains generally to forming thin aluminum oxides at low temperatures, and more particularly to forming uniformly thick, aluminum gate oxides. We disclose a low temperature method for forming a thin, uniform aluminum gate oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; forming a uniformly thick aluminum layer 13; and stabilizing the substrate at a first temperature. The method further includes exposing the aluminum layer to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, aluminum oxide film 16. This method is suitable for room temperature processing.

Abstract: A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.

Abstract: A three-state CMOS output buffer (200), having protective circuitry and an output node (OUT) connected to a bus, prevents damage to a connected integrated circuit when the bus voltage exceeds a power supply reference voltage (VCC). A final output stage of the output buffer (200) includes a first pull-up transistor (QP200), a clamping transistor (QN202), and a pull-down transistor (QN204). A half-pass circuit (QN200) blocks the output voltage from propagating through the final output stage to damage the output buffer (200) when the output voltage applied to the output node (OUT) exceeds the supply voltage. The protective circuitry uses a clamping circuit (210), a switching circuit (212) and a backgate bias circuit (206) to prevent a leakage path between the output node (OUT) and the power supply reference (VCC) through the source/bulk junction of biased transistors in the output buffer (200).