Abstract: A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (10) having a first region (13) and a second region (15). The first region (13) and the second region (15) include a first channel region (14) and a second channel region (16), respectively. A first gate (22) is formed proximate the first channel region (14) and is separated from the substrate (10) by a portion of a primary insulation layer (20). A second gate (24) is formed proximate the second channel region (16) and is separated from the substrate by a portion of the primary insulation layer (20). A dopant layer (34) is then formed outwardly of the substrate (10) proximate the first region (13) and the second region (15). The dopant layer (34) proximate the first region (13) is implanted with a first dopant (40). The dopant layer (34) proximate the second region (15) is implanted with a second dopant (48).

Abstract: A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).

Abstract: A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.

Abstract: A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the steps: forming at least one nucleation region (206/208); masking the at least one narrow silicon structure (202) with a mask (302); treating the at least one nucleation region (206/208) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure (202).

Abstract: A fast FIR filter 100, a system, and a method that increases the operating speed of a filter. The system uses a high order numbering system, in particular Radix-8, and appropriate control lines, parallel data buses 101 and simple circuits for coefficient pre-multiplying. In a typical application, incoming high-speed unequalized 6-bit data are encoded into the high order numbering system, and placed on two data buses 101, one containing the high order data bit stream, e.g., 4 bits for Radix-8, and the other the low order data bit stream, e.g., 3 bits for Radix-8. The data are further encoded in “hot-one” mode so that at all times exactly one bit is asserted. FIR coefficients are calculated, requiring pre-multiplication for only four non-trivial cases in the case of Radix-8 encoding: C, −C, 3C, and −3C, where C is a coefficient value. Because the coefficients do not change at high data rates, high-speed operation of pre-multiplication is not required.

Abstract: An apparatus for extending register dynamic range on a processor is disclosed. The apparatus comprises a register (102) for performing a set of processor (100) operations. The apparatus further comprises a counter (104) on the processor (100) having a value. During the set of operations, the processor (100) increments the value when positive overflow occurs on the register (102) and decrements the value when negative overflow occurs on the register (102). Upon completion of the set of operations, the processor (100) saturates the register (102) with a positive value when the value is greater than zero, and with a negative value when the value is less than zero. Further, a method for extending register dynamic range on a processor is disclosed. The method comprises performing a set of processor (100) operations in a register (102). The method further comprises incrementing a value in counter (104) during the set of operations when positive overflow occurs on the register (102).

Abstract: The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

Abstract: A domino logic circuit (18) comprising a first phase domino logic circuit (20) operable in a precharge phase and an evaluate phase. The first phase domino logic circuit comprises a precharge (20PN) node operable to change states. The domino logic circuit also comprises a second phase domino logic circuit (22) operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the first phase domino logic circuit are out of phase with respect to the precharge phase and an evaluate phase of the second phase domino logic circuit. Further, the second phase domino logic circuit comprises a precharge node (22PN) operable to change states in response to the states of the first phase domino logic circuit.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: An electronic system 8 is disclosed herein. The system includes circuitry 10 for processing a signal and a plurality of antennas 12a-12b. A plurality of switches 22a-22b are also included. Each of the switches 22a-22b is coupled between the processing circuitry 10 and a corresponding one of the antennas 12a-12b. Each of the switches 22a-22b includes first and second power MOSFETs where the source of the first MOSFET is coupled to the source of the second MOSFET. The system further includes circuitry 28 for selecting of one of the plurality of switches 22a-22b to be on.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: A telecommunications gateway allows packets to be sent over a TDM system and allows TDM traffic to be sent over a packet switched network. The gateway is a universal port that includes a plurality of Digital Signal Processors (DSPs) that are controlled by software. The controlling software determines what single function the DSP will perform over multiple channels. Each DSP handles multiple channels, however, each DSP is restricted such that all of its multiple channels are permitted to handle the telecommunications traffic according to one signaling protocol.

Abstract: A system and method for measuring jitter. One class of embodiments is particularly useful for testing the aperture jitter of a high speed Analog to Digital (A/D) converter. Aperture jitter in a Sample and Hold circuit (S/H) or in an A/D converter introduces noise into the sampled signal, which is more extreme in areas of the input waveform that have a steep positive or negative slope. The preferred embodiment allows an easy and inexpensive way to measure aperture jitter in S/H and A/D circuits. The technique can also be adapted for measuring edge jitter in digital clock signals or in analog sine wave signals.

Abstract: A microprocessor based control for monitoring oil pressure of compressors can use a normally open or a normally closed pressure switch (S1, S2) and LED indicator (LED1) having a diode isolated power supply (VDD−SENSOR) separate from the power supply (VDD) of the microprocessor (U1). Timing of the microprocessor is derived from the frequency of the line (60 Hz). The microprocessor is normally in a sleep mode and is awakened by each 60 Hz interrupt to check the condition of the pressure switch, the accumulated time that inadequate pressure has occurred and whether the relay needs to be energized and then returns to the sleep mode. The resulting reduced power requirement enables extended retention of accumulated “bad” oil time.

Abstract: A multi-component electronic assembly (100) including a leadframe (101) having upper and lower surfaces and a plurality of conductive leads (203). Each lead (203) has first bonding surfaces (201) on the upper surface of each lead and second bonding surfaces (201) on the lower surface of each lead (203). Preferably, each lead has a plurality of third bonding surfaces (202) formed on at least some of the plurality of leads where the third bonding surfaces (202) are formed by conductive extensions of the leads (203) that extend towards the center of the assembly (100). A first passive component (102) is electrically and mechanically coupled to the first bonding surfaces. A second passive component (104) is electrically and mechanically coupled to the second bonding surfaces. Where third bonding surfaces (202) are used, a third component (103) is electrically and mechanically coupled to the third bonding surfaces (202).

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal.

Abstract: A data converter (20). The data converter comprises an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises at least one string (12′) of series connected resistive elements (R0′-R14′). The at least one string comprises a plurality of voltage taps (T0′-T14′)and is operable to receive a string bias of X volts (VREF2). Lastly, the data converter comprises a plurality of switching transistors (ST0n-ST15n; ST0p-ST15p) coupled between the plurality of voltage taps and the output. Specifically, responsive to at least a portion of the digital word, selected ones of the switching transistors are operable to receive a gate bias to enable the corresponding switching transistor to provide a conductive path from a corresponding one of the voltage taps toward the output. In addition, the difference between X volts and the gate bias is less than approximately 2.

Abstract: A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.