Abstract: A method of forming a semiconductor device includes forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region, removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.

Abstract: A thermal neutron shield (520) for integrated circuits (511-515) deters absorption of thermal neutrons by circuit constituents to form unstable isotopes with subsequent decay which generates bursts of charge which may upset of stored charge and create soft errors. The shielding may be either at the integrated circuit level (such as a layer on insulation or in the filler of plastic packaging material) or at the board level (such as a filler or film on a container wall).

Abstract: A probe (10) has a main body (12), an input side (14) and an output side (16). The main body (12) has a cavity (17) to receive an insulator (18). The insulator (18) has a current slit (22) and a voltage slit (24) aligned with a first aperture (30a) and a second aperture (30b). An inner conductor extends through the insulator (18) from the input side (14) to the output side (42) of the main body (12). A current sensor (40) inserts into the first aperture (30a) and the current slit (22). A voltage sensor (50) inserts into the second aperture (30b) and the voltage slit (24). A radio frequency signal on a transmission line having a same impedance as the probe (10) enters the inner conductor (20) at the input side (14), induces a current onto the current sensor (40) and a voltage onto the voltage sensor (50). The induced current and voltage can be measured to monitor the characteristics of the transmission line.

Abstract: An adaptive equalizer capable of tracking rapid channel variations while maintaining high stability and low jitter, and a receiver constructed therefrom. A novel feature of the invention is that is that the equalizer is sectioned, that is constructed from a plurality of feed-forward sections and decision-feedback sections, where these sections comprise a cascade of an adaptive linear filter and an adaptive multiplier. This structure is effective at combating rapid channel variations, which are a result of delay variations of the reflections of the signal, e.g., airplane flutter, without sacrificing the stability and the accuracy of the equalizer even in cases where the equalizer has a large number of taps. The different equalizer sections may have different step size parameters. A controller monitors the channel variations and adjusts the step size parameters of each section accordingly.

Abstract: An emitter contact structure, and associated method, for a bipolar junction transistor. The emitter contact structure includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, a base link-up region within the collector region between the intrinsic base region and the extrinsic base region, a base link diffusion source layer above the base link-up region, a capping layer above the base link diffusion source layer, and a base electrode laterally engaging the extrinsic base region.

Abstract: A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: The invention is a method for making a lead frame (30) having fine pitched lead frame leads (32). A first side of the lead frame material is etched to for the lead frame and define the lead frame leads and die pad, but the etch process does not etch completely through the lead frame material. The partially etched first side is then covered with a tape (31) or layer of photoresist (71). The second side of the lead fame material is then etched to complete the lead frame. The lead frame may then be plated.

Abstract: A method for attaching particles (12) to a substrate (14), comprising the steps of aligning particles (12) attached to an adhesive sheet (35) with contact pads (42) of a substrate (14), transferring thermal energy (38) to the adhesive sheet (35) by maintaining a temperature below the melting point of particles (12), and removing the adhesive sheet (35) prior to reflow, is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles may be composed of a variety of compositions, including compounds such as solder or plastic, for example.

Abstract: A method and circuit are presented for operating a polyphase dc motor in which substantially sinusoidal drive voltages are applied to the windings of the motor in predetermined phases. Zero crossings of currents flowing in respective windings of the motor are detected, and phases of the drive voltages are adjusted to have zero crossings substantially simultaneously with the detected zero crossings of the currents flowing in respective windings of the motor. The method and circuit results in motor operation with significantly reduced acoustic motor noise.

Abstract: A dynamic, data-precharged, variable-entry-length content addressable memory circuit architecture. A match at a particular data bit is found employing precharge/conditional discharge domino logic. Two bits stored at each entry location, data bit and valid bit. The valid bit determines whether the corresponding data bit takes part in the match determination. This allows for full flexibility in the matching function including variable-entry-length access. The precharge is data driven. This eliminates clock signal routing to the memory array, reducing crosstalk between clock and data lines and reducing routing congestion. The circuit employs a mix of low threshold voltage and high threshold voltage transistors. The selection of which transistors have low threshold voltage and which have high threshold voltage enables additional speed via low threshold voltage transistors while maintaining low quiescent current via high threshold voltage transistors.

Abstract: The invention is to a device and the method of making circuit devices with side wall contacts produced on a semiconductor wafer (30) by forming grooves (33,34) partially through the wafer surface to provide a plurality of device elements (32) on a common base (31). After the groves are made in the semiconductor wafer, each device element has a top surface (36) and side surfaces (35a-35d). A semiconductor device or integrated circuit is then formed (32) in the top and side surfaces by well know techniques, including diffusing and deposition processes, to form a semiconductor device. Contact pads are formed on both the top and sides of the device to provide a greater density of contacts for the semiconductor device. The semiconductor devices are separated along the grooves (33,34) to provide individual devices.

Abstract: A method for the chemical vapor deposition of titanium aluminum nitride layers. The method includes the steps of placing a substrate in a deposition reactor; introducing tetrakis-dimethyl-amido-titanium (TDMAT) into the reactor; and introducing dimethyl-aluminum-hydride (DMAH) into the reactor in the presence of the TDMAT. In one embodiment the TDMAT is introduced at a rate of between 10 and 1000 times the rate at which the DMAH is introduced. In another embodiment the substrate temperature is between about 200° C. and 500° C.

Abstract: A circuit to process a coded information sequence received from a transmitter, by determining a value for a metric indicative of the relative quality for each of best candidates to be selected as the sequence is actually transmitted, selecting if said coded information sequence is to be decoded in accordance with either E2 PR4 (1,k) or in accordance with EPR4 (0,k); and, using a common trellis to share circuitry between the E2PR4 (1,k) and EPR4 (0,k) detectors to reduce overall complexity.

Abstract: An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).

Abstract: A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.

Abstract: A method of and circuitry for removing noise artifacts in decompressed video signals. A group of pixels is selected from a larger matrix of pixels from adjacent rows and columns of the matrix. A plurality of different subgroups of the group of pixels is selected, each subgroup including the same centrally located pixel. The maximum energy intensity difference emanating from each pixel in each of the subgroups is measured and the maximum difference among the pixels in each subgroup is determined. The subgroup having the lowest maximum difference is selected and the weighed mean of the selected pixels in the subgroup is computed with weights chosen to provide more significance to pixels which are located closer to the centrally located pixel. The centrally located pixel is then filtered with a linear filter, the coefficients of which are determined by the sum of absolute differences between the weighed mean and the pixels in the subgroup.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate of a first conductivity type. A dopant is implanted in one region of the substrate of opposite conductivity type and that region is masked, preferably with a silicon oxide mask. A relatively heavy dose of a dopant of the first conductivity type is implanted in a different region of the substrate while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. The two implants are driven farther into the substrate to form a first tank of said first conductivity type and a second tank of opposite conductivity type by an annealing step while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. A second implant of the first conductivity type is then implanted into the tank of first conductivity type while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type.

Abstract: An adjustable impedance boosting circuit comprises a differential pair of gain stage transistors. A magneto-resistive element may be coupled to the emitters of the gain stage transistors, and a collector load may be coupled to a collector of at least one of the gain stage transistors. The invention further comprises a variable impedance load coupled in parallel with at least a portion of the collector load, the variable impedance load operable to adjust the impedance of the boosting circuit in proportion to the resistance of the magneto-resistive element.

Abstract: A system for wireless communication between a base station 30 and one or more remote stations 32 and 34 wherein a desired signal has associated therewith an identifier tone (a SAT in the vernacular of the AMPS system) and wherein interfering signals may have associated therewith identifier tones at different frequencies. A superresolution technique is used in the system to process the received data and to determine the relative magnitudes of any identifier tones which may be present in the received data. In the disclosed embodiment, the superresolution technique utilized is a least square error process. The resulting estimates are used by the system to facilitate the communication function.