Patents Assigned to Tohoku University
  • Publication number: 20100240283
    Abstract: [Problem] To improve polishing efficiency while lowering shear force added to semiconductor wafers while increasing polishing speed, without damaging the wafer's processing surface or the membrane under it. [Solution Method] Pressing the revolving head or carrier 34 that holds fixed the semiconductor wafer 10 to the polishing pad or polishing cloth 30 attached to rotating polishing table 32 in this CMP device and while rotating carrier 34 and polishing table 32 respectively, and supplying liquid slurry to polishing pad 30 from nozzle 36, planarization by chemical processes and mechanical processes is carried out by removing membranes of the lower face of semiconductor wafer 10 (the processing surface). The chemical mechanical polishing process of the present invention in regard to the size of the relationship between the rotation rate of semiconductor wafer 10 fW and the number of rotations of polishing pad 30 fP has 3 fp<fW as its lower limit and 4 fp<fW<8 fp is ideal conditions.
    Type: Application
    Filed: September 25, 2009
    Publication date: September 23, 2010
    Applicants: ARACA Incorporation, Tokyo Electron Limited, Tohoku University
    Inventors: Takenao Nemoto, Tadahiro Ohmi, Akinobu Teramoto, Xun Gu, Ara Philipossian, Yasa Sampurno
  • Patent number: 7800202
    Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 21, 2010
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto
  • Patent number: 7800673
    Abstract: A solid-state imaging device and an optical sensor, which can enhance a wide dynamic range while keeping a high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping a high sensitivity with a high S/N ratio are disclosed. An array of integrated pixels has a structure wherein each pixel comprises a photodiode PD for receiving light and generating and accumulating photoelectric charges and a storage capacitor element CS coupled to the photodiode PD through a transfer transistor Tr1 for accumulating the photoelectric charges overflowing from the photodiode PD. The storage capacitor element CS is structured to accumulate the photoelectric charges overflowing from the photodiode PD in a storage-capacitor-element accumulation period TCS that is set to be a period at a predetermined ratio with respect to an accumulation period of the photodiode PD.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: September 21, 2010
    Assignee: National University Corporation Tohoku University
    Inventors: Shigetoshi Sugawa, Satoru Adachi, Kyoichi Yahata, Tatsuya Terada
  • Patent number: 7794541
    Abstract: Disclosed is a method of manufacturing a GaN-based material having high thermal conductivity. A gallium nitride-based material is grown by HVPE (Hydride Vapor Phase Epitaxial Growth) by supplying a carrier gas (G1) containing H2 gas, GaCl gas (G2), and NH3 gas (G3) to a reaction chamber (10), and setting the growth temperature at 900 (° C.) (inclusive) to 1,200 (° C.) (inclusive), the growth pressure at 8.08×104 (Pa) (inclusive) to 1.21×105 (Pa) (inclusive), the partial pressure of the GaCl gas (G2) at 1.0×104 (Pa) (inclusive) to 1.0×104 (Pa) (inclusive), and the partial pressure of the NH3 gas (G3) at 9.1×102 (Pa) (inclusive) to 2.0×104 (Pa) (inclusive).
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: September 14, 2010
    Assignees: Tohoku University, Mitsubishi Chemical Corporation
    Inventors: Hiroyuki Shibata, Yoshio Waseda, Kenji Shimoyama, Kazumasa Kiyomi, Hirobumi Nagaoka
  • Patent number: 7789948
    Abstract: Provided is a hydrogen separation membrane characterized by comprising a structure obtained by sintering atomized powder having a composition of NixMyZr100-x-y (wherein M is Nb and/or Ta, 25?x?40, 25?y?40) and an average grain size of 50 ?m or less. The prepared hydrogen separation membrane does not require the use of costly Pd metal, and can be used as a substitute for conventional high-cost bulk metallic glass obtained by quenching of molten metal. This hydrogen separation membrane is free from problems such as defects in the hydrogen separation membrane and unevenness of composition, has a uniform structure, and is capable of separating hydrogen at low cost. Further provided are a sputtering target for forming such as hydrogen separation membrane and its manufacturing method.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: September 7, 2010
    Assignees: Nippon Mining & Metals Co., Ltd, Tohoku University
    Inventors: Atsushi Nakamura, Masataka Yahagi, Akihisa Inoue, Hisamichi Kimura, Shin-ichi Yamaura
  • Publication number: 20100220754
    Abstract: A method of driving an ultrashort pulse and ultrahigh power laser diode device having a simple composition and a simple structure is provided. In the method of driving a laser diode device, light is injected from a light injection means into a laser diode device driven by a pulse current having a value 10 or more times as large as a value of a threshold current.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 2, 2010
    Applicants: Sony Corporation, Tohoku University
    Inventors: Hiroyuki Yokoyama, Shunsuke Kono, Tomoyuki Oki, Masao Ikeda
  • Patent number: 7787076
    Abstract: As a shape on a cross-section vertical to a longitudinal direction (L) of the hot cathode fluorescent lamp (20a (20b)), a light source rear side reflecting plane (62) of a reflector (60) includes a mound portion (623). The mound portion (623) is defined by two recessed inclining planes and protrudes toward a hot cathode fluorescent lamp (20a (20b)).
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: August 31, 2010
    Assignee: Tohoku University
    Inventors: Tadahiro Ohmi, Yasuyuki Shirai, Kiwamu Takehisa
  • Patent number: 7782413
    Abstract: The present invention includes a liquid crystal display device with an oxide film having high adhesiveness to a semiconductor layer or a pixel electrode to thereby prevent oxidation of a wiring material or the like, and includes a source electrode and a drain electrode having high conductivity, and a manufacturing method therefor. In one embodiment of the present invention, a liquid crystal display device has a TFT electrode of a TFT substrate, wherein a source electrode or a drain electrode includes a layer of mainly copper and an oxide covering an outer part of the layer. Further, in the present invention, the semiconductor layer or the pixel electrode and said source electrode or the drain electrode are in ohmic contact in the TFT electrode.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: August 24, 2010
    Assignees: Tohoku University, Advanced Interconnect Materials LLC
    Inventors: Junichi Koike, Hideaki Kawakami
  • Patent number: 7782433
    Abstract: A method of forming an oxide film on a surface of a copper alloy, including the steps of providing a copper alloy including copper and an element selected from the group consisting of Mn, Zn, Ga, Li, Ge, Sr, Ag, Ba, Pr and Nd, and diffusing atoms of the element to a surface of the copper alloy so as to form an oxide film on the surface of the copper alloy, wherein a concentration of the element in the copper alloy is more than 0.1 and not more than 20 atomic percentage and within a solubility limit of the element in the copper.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: August 24, 2010
    Assignees: Tohoku University, Advanced Interconnect Materials LLC
    Inventor: Junichi Koike
  • Publication number: 20100201901
    Abstract: The present invention includes a liquid crystal display device with an oxide film having high adhesiveness to a semiconductor layer or a pixel electrode to thereby prevent oxidation of a wiring material or the like, and includes a source electrode and a drain electrode having high conductivity, and a manufacturing method therefor. In one embodiment of the present invention, a liquid crystal display device has a TFT electrode of a TFT substrate, wherein a source electrode or a drain electrode includes a layer of mainly copper and an oxide covering an outer part of the layer. Further, in the present invention, the semiconductor layer or the pixel electrode and said source electrode or the drain electrode are in ohmic contact in the TFT electrode.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Applicants: Tohoku University, Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Hideaki Kawakami
  • Publication number: 20100188186
    Abstract: A soft magnetic amorphous alloy represented by the following composition formula: {Fea(SixByPz)1-a}100-bLb. In the composition formula, L represents one or more elements selected from Al, Cr, Zr, Nb, No, Hf, Ta and W, and a, b, x, y, and z meets the conditions of: 0.7?a?0.82; 0?b?5 atomic %; 0.05?x?0.6; 0.1?y?0.85; 0.05?z?0.7; and x+y+z=1.
    Type: Application
    Filed: September 16, 2008
    Publication date: July 29, 2010
    Applicants: NEC Tokin Corporation, Tohoku University
    Inventors: Akiri Urata, Hiroyuki Matsumoto, Akihiro Makino
  • Patent number: 7764355
    Abstract: A stage body has a holding surface for placing a substrate thereon. A predetermined embossed configuration is formed by embossing on the holding surface, and thereafter an alumina film in an amorphous state is formed by an anodic oxidation process on the holding surface. The alumina film having an amorphous structure is dense and strong to provide high wear resistance and to substantially prevent separation electrification. This provides a substrate stage having high wear resistance and capable of preventing separation electrification.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 27, 2010
    Assignees: Tohoku University, Future Vision Inc.
    Inventors: Tadahiro Ohmi, Yusuke Muraoka, Yasuyoshi Miyaji, Yasushi Nagashima
  • Patent number: 7764763
    Abstract: It is an object of the present invention to eliminate windmill artifacts that inevitably occurs when a helical scan is performed with an X-ray CT system. To this end, the present invention is equipped with an X-ray source, and an X-ray detector having a plurality of detector elements arranged two-dimensionally, and disposed opposite to the X-ray source with a predetermined rotation center axis therebetween. The invention further includes reconstruction means for performing an arithmetic operation, in which two-dimensional projection data obtained based on X-ray detection data detected by the detector elements while rotating the X-ray source around the rotation center axis are back projected along a path different in a Z-axis direction extending along the rotation center axis from the X-ray path of the projection data, to reconstruct an image.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 27, 2010
    Assignee: Tohoku University
    Inventor: Issei Mori
  • Publication number: 20100182470
    Abstract: A pixel output line (14) is independently provided for each of the pixels arranged in a two-dimensionally array within a pixel area so that pixel signals can be sequentially written in a plurality of memory sections (22) through the pixel output lines (14). When a plurality of frames of pixel signals are held in the memory sections (22), the pixel signals corresponding to two arbitrarily selected frames are read and respectively stored in sample-and-hold circuits (61 and 62), and their difference is obtained. Then, the difference signals corresponding to a predetermined range of the image are integrated, and the integrated value is compared with a threshold. If the integrated value exceeds the threshold, it is presumed that a change in an imaging object has occurred, and a pulse generation circuit (66) generates a trigger signal.
    Type: Application
    Filed: September 4, 2008
    Publication date: July 22, 2010
    Applicants: Tohoku University, Shimadzu Corporation
    Inventors: Shigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
  • Patent number: 7759750
    Abstract: To provide a highly-reliable, low-power-consumption nonvolatile memory. A magnetization reversal of a ferromagnetic free layer is accomplished with a spin transfer torque in a state where an appropriate magnetic field is applied in a direction orthogonal to the direction of the magnetic easy axis of the ferromagnetic free layer of the tunnel magnetoresistance device that the magnetic memory cell includes. Preferably, the magnetic field is applied in a direction forming an angle of 45° with the direction perpendicular to the film plane.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: July 20, 2010
    Assignees: Hitachi, Ltd., Tohoku University
    Inventors: Jun Hayakawa, Hideo Ohno, Shoji Ikeda
  • Patent number: 7758805
    Abstract: A hydrogen occlusive alloy has a cubic structure and a composition represented by the following general formula (1): (Mg1-XLX)(Ni1-Y-ZMYLiZ)m??(1) where the element L is at least one element selected from the group consisting of Na, Cs, Ca, Sr, Ba, Sc, Ti, Zr, Hf, V, Nb, Ta, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, the element M is at least one element selected from the group consisting of Cr, Mo, W, Mn, Fe, Co, Pd, Pt, Cu, Ag, Zn, Cd, B, Al, Ga, In, Si, Ge, Sn, Pb, Sb and Bi, and mole ratios X, Y, Z and m are 0<X?0.5, 0<Y?0.5, 0.1?Z?0.9, and 1.8?m?2.2, respectively.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: July 20, 2010
    Assignees: Kabushiki Kaisha Toshiba, Tohoku University
    Inventors: Tatsuoki Kohno, Shin-ichi Orimo, Yuko Nakamori
  • Patent number: 7755192
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol: Cu). The barrier layer is located between the insulating layer and the interconnection. The barrier layer includes an additional element, carbon (element symbol: C) and hydrogen (element symbol: H). The barrier layer has atomic concentrations of carbon (element symbol: C) and hydrogen (element symbol: H) maximized in a region of a thickness of the barrier layer where the atomic concentration of the additional element is maximized.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: July 13, 2010
    Assignees: Tohoku University, Advanced Interconnect Materials LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Publication number: 20100162945
    Abstract: A method to make gallium nitride-based material by Hydride Vapor Phase Epitaxial Growth is provided.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Applicants: Tohoku University, Mitsubishi Chemical Corporation
    Inventors: Hiroyuki Shibata, Yoshio Waseda, Kenji Shimoyama, Kazumasa Kiyomi, Hirobumi Nagaoka
  • Publication number: 20100154213
    Abstract: A method for forming a copper interconnection structure includes the steps of forming an opening in an insulating layer, forming a copper alloy layer including a metal element on an inner surface of the opening, and conducting a heat treatment on the copper alloy layer so as to form a barrier layer. An enthalpy of oxide formation for the metal element is lower than the enthalpy of oxide formation for copper. The heat treatment is conducted at temperatures ranging from 327° C. to 427° C. and for a time period ranging from 1 minute to 80 minutes.
    Type: Application
    Filed: October 28, 2009
    Publication date: June 24, 2010
    Applicants: Tohoku University, Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Publication number: 20100155951
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.
    Type: Application
    Filed: October 29, 2009
    Publication date: June 24, 2010
    Applicants: Tohoku University, Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi