Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 11715778
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, and third semiconductor regions. The third electrode is between the first electrode and the second electrodes. The first semiconductor region includes Alx1Ga1-x1N and includes first to seventh partial regions. The fourth partial region is between the first partial region and the third partial region. The fifth partial region is between the third partial region and the second partial region. The second semiconductor region includes Alx2Ga1-x2N and includes first and second semiconductor portions. The sixth partial region is between the fourth partial region and the first semiconductor portion. The seventh partial region is between the fifth partial region and the second semiconductor portion. The third semiconductor region includes Alx3Ga1-x3N and includes a first semiconductor film part. The first semiconductor film part is between the sixth partial region and the third electrode.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 1, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Mukai, Masahiko Kuraguchi
  • Patent number: 11715776
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 1, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Keiko Kawamura
  • Patent number: 11715796
    Abstract: A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 1, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Mitsutoshi Nakamura, Kazuya Nishihori, Keita Masuda
  • Publication number: 20230238944
    Abstract: According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode.
    Type: Application
    Filed: July 12, 2022
    Publication date: July 27, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsunori SAKANO, Ryohei GEJO, Tomoko MATSUDAI
  • Patent number: 11710501
    Abstract: A magnetic head includes a first magnetic pole, a second magnetic pole, a magnetic element, and a magnetic member. The magnetic element is provided between the first and second magnetic poles, and includes a first magnetic layer. The magnetic member includes a first magnetic part. A second direction from the first magnetic part to the magnetic element crosses a first direction from the first to second magnetic pole. The first magnetic part includes a magnetic material including at least one of first to third materials. The first material includes at least one selected from the group consisting of Mn3Sn, Mn3Ge and Mn3Ga. The second material includes at least one selected from the group consisting of a cubic or tetragonal compound including Mn and Ni, a cubic alloy including ?-phase Mn, and a cubic alloy including Fe. The third material includes an antiferromagnet.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: July 25, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuji Nakagawa, Naoyuki Narita, Masayuki Takagishi, Tomoyuki Maeda, Tazumi Nagasawa, Kenichiro Yamada, Akira Kikitsu
  • Patent number: 11709516
    Abstract: A power supply circuit in an embodiment includes a series circuit of a first resistor and a second transistor, the series circuit being connected in parallel to a first transistor between an input terminal and an output terminal, a third transistor configured to output an electric current corresponding to an electric current flowing to the first resistor, a third resistor configured to generate a voltage corresponding to the electric current, and a second operational amplifier configured to output a signal corresponding to a voltage difference between the voltage and a reference voltage to a gate of the first transistor and a gate of the second transistor.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: July 25, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Chen kong Teh
  • Patent number: 11710507
    Abstract: According to one embodiment, a disk device includes a plurality of recording media each including a recording layer and an actuator assembly including an actuator block rotatably supported around a rotation shaft, a plurality of arms extending from the actuator block, and suspension assemblies respectively attached to the arms and supporting respective magnetic heads. Of the plurality of arms, at least one arm has vibration characteristics different from those of the other arms.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: July 25, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tomoyuki Tokizaki
  • Patent number: 11710750
    Abstract: A semiconductor device includes element regions which each include a first region of a first conductivity type, a second region of the first conductivity type on the first region and having a higher impurity concentration than that of the first region, a third region of a second conductivity type on the second region. The second region is between the first and third regions in a first direction. A first insulating portion surrounds each element region in a first plane. A fourth region of the first conductivity type surrounds each element region and the first insulating portion in the first plane. The fourth region has a higher impurity concentration than that of the first region. A quenching structure is above a part of the fourth region in the first direction and electrically connected to the third region.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 25, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Mitsuhiro Sengoku, Nobu Matsumoto, Koichi Kokubun
  • Patent number: 11705152
    Abstract: A magnetic head includes a first magnetic pole, a second magnetic pole, and a stacked body provided between the first and second magnetic poles. The stacked body includes a first magnetic member, a second magnetic member provided between the first magnetic member and the second magnetic pole, a first layer provided between the first and second magnetic members, and a second layer provided between the second magnetic member and the second magnetic pole. The first magnetic member includes first magnetic regions and a first nonmagnetic region. The first nonmagnetic region is between the one of the first magnetic regions and the other one of the first magnetic regions.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hitoshi Iwasaki, Naoyuki Narita, Hirofumi Suto, Masayuki Takagishi, Tazumi Nagasawa
  • Patent number: 11705442
    Abstract: According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: July 18, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Atsushi Hosokawa, Yasuhisa Shintoku, Yasukazu Noine, Yoshiharu Katayama
  • Patent number: 11705334
    Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuhki Fujino
  • Patent number: 11705447
    Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Kenya Kobayashi
  • Patent number: 11705438
    Abstract: A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tatsuya Hirakawa
  • Patent number: 11705154
    Abstract: According to an embodiment, a manufacturing method includes: estimating a distribution of an initial value of a clearance of a magnetic head on a first recording surface; and recording first spiral signals on the first recording surface while controlling a clearance using the distribution of the initial value of the estimated clearance. The manufacturing method includes measuring a distribution of an initial value of a clearance of a magnetic head on a second recording surface under positioning control using the first spiral signals recorded on the first recording surface. The manufacturing method includes recording the first spiral signals on the second recording surface while controlling a clearance using the distribution of the initial value of the measured clearance of the magnetic head on the second recording surface.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takahiro Magome, Satoshi Yamashita, Takahiro Aoki
  • Patent number: 11703575
    Abstract: A photodetector includes a plurality of channels each having a plurality of SPAD units, each SPAD unit having an avalanche photodiode. The photodetector is capable of selecting outputting or non-outputting of the channels. The SPAD unit includes: an active quenching circuit which performs active quenching of the avalanche photodiode; and a control circuit which brings the active quenching circuit which corresponds to the channel where non-outputting is selected into an operable state.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Kubota, Nobu Matsumoto
  • Patent number: 11706854
    Abstract: LED drive control circuitry according to one embodiment outputs an LED drive control signal serving as driving a light emitting diode included in a photocoupler that performs insulation communication in synchronization with a reference clock signal. The LED drive control circuit includes a duty cycle changer that changes a duty cycle of the LED drive control signal in accordance with the reference clock signal and a signal synchronized with the reference clock signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 18, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Katsuyuki Ikeuchi
  • Patent number: 11699459
    Abstract: According to one embodiment, a magnetic disk includes a disk, first and second heads which write data to the disk and read data from the disk, a first actuator includes the first head, a second actuator includes the second head, first and second controllers which control the first head, the second head, the first actuator and the second actuator, an auxiliary power supply which supplies power when power from a power supply is shut off, and a power supply detection unit which makes power supplied from the auxiliary power supply to the first controller higher than the power supplied from the auxiliary power supply to the second controller when shutoff of power from the power supply is detected.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: July 11, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuki Kawamitsu
  • Patent number: 11699692
    Abstract: A semiconductor device includes a first switching element, a second switching element, an optical coupling element, a plurality of leads and an outer resin member. The first switching element includes a first semiconductor chip and a first inner resin member sealing the first semiconductor chip. The second switching element includes a second semiconductor chip and a second inner resin member sealing the second semiconductor chip. The optical coupling element includes a light-emitting element, a light-receiving element and a third inner resin member sealing the light-emitting element and the light-receiving element. The first and second switching element and the optical coupling element are provided with terminals projecting from the first to third inner resin member, and the plurality of leads are electrically connected to the terminals. The outer resin member seals the first and second switching elements, the optical coupling element, and the plurality of leads.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: July 11, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Takamitsu Noda
  • Patent number: 11694715
    Abstract: A head suspension assembly includes a support plate, a wiring member on the support plate, a head mounted on the wiring member and electrically connected to the wiring member, and a piezoelectric element mounted on the wiring member. The piezoelectric element has first and second electrodes electrically connected to the wiring member. The wiring member includes a metal layer, a base insulating layer, a conductive layer, and a cover insulating layer stacked in order. The cover insulating layer includes a pad opening through which the first electrode is connected to the conductive layer with a conducive adhesive therebetween. The base insulating layer includes a first region below the first pad opening and a second region below a side surface of the piezoelectric element. A thickness of the base insulating layer in the second region is less than a thickness of the base insulating layer in the first region.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: July 4, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yasuo Suzuki, Takuma Kido
  • Patent number: 11695043
    Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 4, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenya Kobayashi