Abstract: A method for positioning a magnetic head having first and second read sensors and one write head includes: while the magnetic head is at a first position relative to a disk medium, reading first magnetic servo information written on a first surface of the disk medium, with the first read sensor, and reading second magnetic servo information written on the first surface of the disk medium with the second read sensor; determining a position error of the magnetic head based on the first and second magnetic servo information; and repositioning the magnetic head to a second position relative to the disk medium to compensate for the determined position error of the magnetic head.

Abstract: According to an embodiment, a magnetic disk device includes a magnetic disk, a spindle motor that rotates the magnetic disk, a motor driver, and a controller. The motor driver supplies a motor current to the spindle motor and measures a counter electromotive voltage of the spindle motor every time the spindle motor makes one rotation. After the rotation of the magnetic disk starts, the controller adjusts a motor position where the counter electromotive voltage is measured to a set first position.

Abstract: According to one embodiment, a light detector includes: a first set of light detection elements and a second set of light detection elements each being disposed in a first region on a substrate; and a first selection and integration circuit and a second selection and integration circuit each being disposed in a second region outside of the first region on the substrate. The first selection and integration circuit is configured to select a first subset of light detection elements in the first set, and integrate outputs from the light detection elements in the first subset. The second selection and integration circuit is configured to select a second subset of light detection elements in the second set, and integrate outputs from the light detection elements in the second subset.

Abstract: A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.

Abstract: A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first end, a second end, and a first body. The second transistor includes a third end coupled to the second end, a fourth end, and a second body. The semiconductor device includes a first resistor coupled to the first end, a second resistor coupled between the first resistor and the second end, a third resistor coupled to the third end, a fourth resistor coupled between the third resistor and the fourth end, a first diode coupled between the first body and a node coupling the third resistor and the fourth resistor, and a second diode coupled between the second body and a node coupling the first resistor and the second resistor.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.

Abstract: A semiconductor device includes a semiconductor layer, first and second electrodes, one or more gate electrodes, and an array of structures. The semiconductor layer has first and second sides opposite to each other in a first direction. The semiconductor layer is single crystal silicon. The array of structures is in the semiconductor layer and arranged in a second direction perpendicular to the first direction and along a [100] direction of the single crystal silicon and in a third direction that is perpendicular to the first direction and not perpendicular to the second direction. A first distance between first and second ones of the structures adjacent to each other in the third direction is less than a second distance between the first one and a third one of the structures adjacent to the first one in the second direction.

Abstract: According to one embodiment, a semiconductor device includes a lead frame including a terminal; an element on a first surface of the lead frame; and a package member covering the lead frame and the semiconductor element. The terminal includes a back-side portion provided on a side of a second surface of the lead frame and exposed from the package member in a first direction perpendicular to the first surface, the second surface being opposite to the first surface, a lateral-side portion provided between the first surface and the back-side portion in the first direction and exposed from the package member in a second direction parallel to the first surface, and a recessed portion provided between the lateral-side portion and the back-side portion in the first direction.

Abstract: According to one embodiment, a semiconductor device includes a package substrate including a package member and a first conductive portion; a semiconductor package provided on a first surface of the package substrate inside the package member and coupled to the first conductive portion; a first semiconductor chip provided on the first surface of the package substrate inside the package member and including a first terminal; a second semiconductor chip provided on the first surface of the package substrate inside the package member and including a second terminal; and a connection component that couples the first and second terminals to the first conductive portion inside the package member.

Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.

Abstract: A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied, S1<S3, S1<S2, S3>S4.

Abstract: Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second

Abstract: A semiconductor device includes: a first insulating film provided in a trench reaching a second semiconductor layer from above the second semiconductor region; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; the second insulating film being provided between the side surface of the second electrode and a fifth insulating film provided between a side surface of the second electrode and the second semiconductor layer, the second insulating film containing a second insulating material having a higher dielectric constant than the first insulating material; a third electrode provided above the second electrode, the first insulating film and the second insulating film, the third electrode facing the first semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided above the interlayer insulating film.

Abstract: According to one embodiment, a semiconductor device includes an n-layer and a p-layer arranged in a vertical trench structure in a drift layer. A depletion layer is formed to a depth of a trench of the vertical trench structure after a depletion layer spreads in a lateral direction between the n-layer and the p-layer when a voltage is applied between a drain and a source. A method for controlling the semiconductor device comprises detecting a voltage value between the drain and the source of the semiconductor device at turn-off and reducing a current value of a gate discharge current discharged from a gate in a first period. The first period starting before the detected voltage value greatly changes.

Abstract: A semiconductor device includes a semiconductor part, first and second electrodes and first-third and second-third electrodes. The semiconductor part is provided between the first and second electrodes. The semiconductor part includes a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type. The second and third semiconductor layers are arranged between the first layer and the second electrode. The first-third and second-third electrodes are provided in the semiconductor part. The second semiconductor layer is provided between the first-third electrode and the second-third electrode. The second electrode includes a contact portion extending into the second semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer between the contact portion and the second-third electrode. The second semiconductor layer includes a first portion facing the third semiconductor layer via the contact portion.

Abstract: In one embodiment, electronic circuitry includes a driving circuit that is configured to: supply a driving current to a control terminal of a first switching element; and increase the driving current in accordance with a first time at which a current flowing through a second switching element connected to a first terminal or a second terminal of the first switching element becomes 0.

Abstract: According to one embodiment, electronic circuitry includes a transmission circuit to output a waveform including a plurality of pulse waveforms in response to an input signal. The pulse waveforms include a first transmit pulse waveform, and a second transmit pulse waveform following the first transmit pulse waveform, and the first transmit pulse waveform is larger in amplitude than the second transmit pulse waveform.

Abstract: A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each of the unit element regions includes a first semiconductor part, a second electrode, and a first conductive part. The first semiconductor part includes first to third semiconductor regions. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The first conductive part faces the second semiconductor region via a first insulating film. At least a portion of the plurality of unit element regions includes a common pattern. The partitioning region includes a second semiconductor part and partitions the plurality of unit element regions. The second semiconductor part is continuous with the first semiconductor part.

Abstract: According to one embodiment, electronic circuitry includes: transmitting circuitry to output a first waveform including N pulse waveforms (N is a natural number larger than 1) in response to an input signal; transfer circuitry to transfer the first waveform as a second waveform that includes at least N+1 pulse waveforms, via electromagnetic coupling; and receiving circuitry configured to receive the second waveform and determine the input signal based on the at least N+1 pulse waveforms.