Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Publication number: 20230299129
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type; a semiconductor layer located on the semiconductor substrate, the semiconductor layer being of the first conductivity type and including a first device part; a buried layer located between the semiconductor substrate and the first device part, the buried layer being of a second conductivity type; a guard region located at a first-direction side of the first device part, the guard region being of the second conductivity type, a lower end of the guard region contacting the buried layer, an upper end of the guard region reaching an upper surface of the semiconductor layer, the guard region not being located at a second-direction side of the first device part, the second direction being opposite to the first direction; and a first semiconductor region located inside the first device part and being of the second conductivity type.
    Type: Application
    Filed: September 8, 2022
    Publication date: September 21, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kanako KOMATSU, Yoshiaki ISHII, Daisuke SHINOHARA
  • Publication number: 20230297131
    Abstract: In one embodiment, electronic circuitry comprises a first circuit capable of transmitting and receiving signals, a second circuit capable of transmitting and receiving signals, and an insulation element. The first circuit has a first terminal to which a first clock signal is input, increases the frequency of the first clock signal to generate a second clock signal, and transmits the second clock signal. The insulation element transmits the second clock signal obtained from the first circuit to the second circuit as a third clock signal. The second circuit receives the third clock signal from the insulation element, and transmits a first data signal in response to the third clock signal. The insulation element transmits the first data signal obtained from the second circuit as a second data signal. The first circuit receives the second data signal from the insulation element.
    Type: Application
    Filed: September 6, 2022
    Publication date: September 21, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kaili WANG, Hiroaki ISHIHARA
  • Patent number: 11764132
    Abstract: A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: September 19, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Haruhiko Iwabuchi
  • Patent number: 11764141
    Abstract: A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: September 19, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shun Takeda
  • Patent number: 11756863
    Abstract: According to an embodiment, provided is a semiconductor device includes a semiconductor layer; a first electrode; a second electrode; an electrode pad; a wiring layer electrically connected to the gate electrode; a first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer; and an insulating layer provided between the first polycrystalline silicon layer and the electrode pad and between the first polycrystalline silicon layer and the wiring layer and having a first opening and a second opening. The electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the first opening. The wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the second opening, A first opening area of the first opening is larger than a second opening area of the second opening.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Kono
  • Patent number: 11756791
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
  • Patent number: 11757624
    Abstract: According to an embodiment, a data transfer control device includes a controller, and the controller generates tag information when the controller receives a tag generation request, and encrypts the tag information, transmits the encrypted tag information to a device that transmits the tag generation request, processes data stored at a predetermined address to generate data for transmission when an address at which the data related to the data transfer request is stored includes the predetermined address, scrambles or encrypts the data for transmission using the tag information, and transmits the scrambled or encrypted data to the device.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 12, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yasuto Aramaki
  • Patent number: 11756580
    Abstract: A magnetic disk device includes a plurality of magnetic heads, a storage unit that stores a table storing, for each of the magnetic heads, a track skew value obtained by adding a head shared value and a head unique value, and a control unit that reads out the track skew value corresponding to one of the magnetic heads to be operated from the table and performs seek control.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Sho Suzuki, Takayuki Kawabe, Takeyori Hara, Daisuke Sudo
  • Patent number: 11756986
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Ishiguro, Ryohei Nega, Yoshihiko Fuji
  • Patent number: 11757028
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 12, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20230282996
    Abstract: According to an embodiment, an electronic device includes a substrate and an electronic component. The substrate includes a first surface facing a first direction and to which a first hole and a second hole are open. The electronic component includes a base, a first protrusion in the first hole, and a second protrusion in the second hole. The first protrusion and the second protrusion protrude from the base. The first end of the first protrusion is more apart from the first surface than the second end of the second protrusion. The first protrusion and the second protrusion have a first inclined surface and a second inclined surface extending obliquely with respect to the first direction. In a third direction orthogonal to the first direction the first inclined surface is longer in length than the second inclined surface.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 7, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kiyokazu ISHIZAKI, Masahide TAKAZAWA, Nobuhiro YAMAMOTO
  • Patent number: 11749722
    Abstract: A semiconductor device of embodiments includes a silicon carbide layer having a first face and a second face, a gate electrode, a gate insulating layer on the first face. The silicon carbide layer includes a first silicon carbide region of a first conductive type; a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face; a third silicon carbide region of a second conductive type between the first silicon carbide region and the first face; a fourth silicon carbide region; a fifth silicon carbide region; a sixth silicon carbide region of a second conductive type between the first silicon carbide region and the first face and between the second silicon carbide region and the third silicon carbide region; and a crystal defect. The crystal defect is in the sixth silicon carbide region.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takuma Suzuki, Sozo Kanie, Chiharu Ota, Susumu Obata, Kazuhisa Goto
  • Patent number: 11747427
    Abstract: A distance measuring device according to an embodiment includes a first device including a first transceiver configured to transmit a first known signal and a second known signal and receive a third known signal corresponding to the first known signal and a fourth known signal corresponding to the second known signal, a second device including a second transceiver configured to transmit the third known signal and the fourth known signal and receive the first and second known signals and a calculating section configured to calculate a distance between the first device and the second device on a basis of phases of the first to fourth known signals, and the first transceiver and the second transceiver transmit/receive the first and third known signals one time each and transmit/receive the second and fourth known signals one time each, performing transmission/reception a total of four times.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: September 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masaki Nishikawa
  • Patent number: 11749308
    Abstract: A disk device includes magnetic disks, ramps, suspensions, and magnetic disks. The magnetic disks are arranged above a housing bottom and configured to be rotated around a first rotation axis. The ramps are arranged above the housing bottom. The suspensions are configured to be rotated around a second rotation axis parallel to the first rotation axis, The magnetic heads are mounted on the suspensions, respectively. Each of the suspensions is configured to be rotated around the second rotation axis from a first position above or below one of the magnetic disks to a second position on one of the ramps. The plurality of ramps includes a first ramp and a second ramp that is above the first ramp. An inner end of the second ramp is closer to the first rotation axis than is an inner end of the first ramp.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: September 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yasuhiko Kato
  • Patent number: 11747367
    Abstract: A current sensor of an embodiment includes a U-shaped conductor through which a current flows, a first magnetic field sensor configured to receive a magnetic field generated by the conductor in a first direction, and a second magnetic field sensor configured to receive the magnetic field in a second direction opposite to the first direction.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: September 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Jia Liu
  • Publication number: 20230267961
    Abstract: According to one embodiment, a magnetic head includes first and second magnetic poles, a stacked body, and first to third terminals. The stacked body is provided between the first and second magnetic poles. The stacked body includes a first magnetic layer, a second magnetic layer between the first magnetic layer and the second magnetic pole, a third magnetic layer between the second magnetic layer and the second magnetic pole, a fourth magnetic layer between the third magnetic layer and the second magnetic pole, a first nonmagnetic layer between the first magnetic pole and the first magnetic layer, a second nonmagnetic layer between the first and second magnetic layers, a third nonmagnetic layer between the second and third magnetic layers, a fourth nonmagnetic layer between the third and fourth magnetic layers and a fifth nonmagnetic layer between the fourth magnetic layer and the second magnetic pole.
    Type: Application
    Filed: August 10, 2022
    Publication date: August 24, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tazumi NAGASAWA, Yuji NAKAGAWA, Naoyuki NARITA, Masayuki TAKAGISHI, Tomoyuki MAEDA, Ryo OSAMURA
  • Publication number: 20230268430
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 24, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu KATO, Yosuke KAJIWARA, Akira MUKAI, Aya SHINDOME, Hiroshi ONO, Masahiko KURAGUCHI
  • Patent number: 11733970
    Abstract: An artificial intelligence system includes a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function. The arithmetic operation circuit includes a first circuit configured to perform an exponent arithmetic operation using a Napier's constant e as a base and output a first calculation result when an exponent in the exponent arithmetic operation is a negative number, wherein an absolute value of the exponent is used in the exponent arithmetic operation, and a second circuit configured to subtract the first calculation result obtained by the first circuit from 1 and output the subtracted value.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: August 22, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masanori Nishizawa
  • Patent number: 11735209
    Abstract: According to one embodiment, a magnetic disk device, including a disk, a head to write data to the disk and read data from the disk, a preamplifier to generate a recording current corresponding to data that the head writes to the disk, and a controller to convert a first data pattern in first write data, in accordance with a pattern length of a second data pattern previous to the first data pattern, to a different data pattern including a pseudo polarity inversion that does not cause a polarity inversion when converting the first data pattern to the recording current.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 22, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tomokazu Okubo
  • Patent number: 11735221
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a read head that reads data from the disk, a write head that writes data to the disk, and an assist element that generates energy to enhance write performance by the write head, and a controller that selects and performs a first recording mode and a second recording mode different from the first recording mode, and selects and performs one of the first recording mode and the second recording mode according to an assist effect of the assist element.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: August 22, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yusuke Tomoda