Abstract: Embodiments of exponent processing systems and methods are disclosed. One method embodiment, among others, comprises performing a first table lookup using a first address to provide a first value corresponding to the first component part, setting an integer exponent to provide an integer-based value corresponding to the integer component, performing a second table lookup using a second and third address to provide a second value and a third value corresponding to the second component part and the third component part, respectively, expanding and normalizing the second and third values to provide expanded and normalized second and third values, combining the expanded and normalized second and third values to produce a first product, and computing the exponential function by combining the first value, the integer-based value, and the first product.

Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.

Abstract: The invention provides a method for improving efficiency of a filter bank. The filter bank includes multiple filters implemented by a firmware program. Each of the filters has a corresponding filter equation with a plurality of variables including a plurality of input samples and output samples of the corresponding filter. The variables of the filters are first stored in a specific order, wherein the variables of the same filter are stored together and the input samples and the output samples are stored separately and sorted according to a time index thereof. A starting pointer is then pointed to a first variable of a first filter of the filters. A plurality of current output samples of the filters is then generated according to the filter equations, the variables stored in the specific order, and a plurality of current input samples of the filters. The variables of the filter equations are then updated with the current input samples and the current output samples according to the specific order.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: A channel memory length selection method for wireless communication systems is provided. The method comprises estimating an initial channel impulse response (CIR) for the wireless communication system; determining a first refined CIR with a first group of taps and a second refined CIR with a second group of taps based upon the initial CIR, number of the second group of taps being less than number of the first group of taps; and selecting either the number of the first group of taps or the number of the second group of taps as the channel memory length according to an energy concentration criterion in regard to the first refined CIR and the second refined CIR.

Abstract: A method and system are disclosed for synchronizing two or more engines in a graphics processing unit (GPU). When issuing a command to an engine, a central processing unit (CPU) writes an event value representing the command into an element of an event memory associated with the engine. After executing the command, the engine modifies the content of the event memory in order to recognize the completion of the command execution. The CPU acquires the command execution status by reading the modified content of the event memory. With precise knowledge of the command execution status, the CPU can issue commands to various engines independently, hence the engines can run parallel.

Abstract: A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch instructions within the fetch quantum (N is at least two), updates the BTAC for the branch instruction if the BTAC is not already storing information for N branch instructions, determines whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions if the BTAC is already storing information for N branch instructions, and updates the BTAC for the branch instruction if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.

Abstract: A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

Abstract: Various embodiments for reducing external bandwidth requirements for transferring graphics data are included. One embodiment includes a system for reducing the external bandwidth requirements for transferring graphics data comprising a prediction error calculator configured to generate a prediction error matrix for a pixel tile of z-coordinate data, a bit length calculator configured to calculate the number of bits needed to store the prediction error matrix, a data encoder configured to encode the prediction error matrix into a compressed block and a packer configured to shift the compressed block in a single operation to an external memory location.

Abstract: A method and device of automatic detection and modification of subtitle position comprises the steps of comparing an active display area parameter of a displaying device to an original subtitle control signal to generate a comparison result, and outputting a targeted subtitle control signal to modify the position of the subtitle depends on the comparison result so that the subtitle is guaranteed to display in the active display area. Accordingly, the subtitle position detection and modification method and device may not only as a solution of improper subtitle display position arrangement, but also excite the viewer's joy of the sight and eliminate the inconvenience of the complicated adjusting operations.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus for performing cryptographic operations. The apparatus includes an x86-compatible microprocessor that has fetch logic, algorithm logic, and execution logic. The fetch logic is configured to receive a single, atomic cryptographic instruction as one of the instructions in an application program executing on the x86-compatible microprocessor. The single, atomic cryptographic instruction prescribes an encryption operation and one of a plurality of cryptographic algorithms. The algorithm logic is operatively coupled to the single, atomic cryptographic instruction. The algorithm logic directs the x86-compatible microprocessor to execute the encryption operation according to the one of a plurality of cryptographic algorithms. The execution logic is operatively coupled to the algorithm logic. The execution logic executes the encryption operation. The execution logic includes a cryptography unit for executing a plurality of cryptographic rounds required to complete the encryption operation.

Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Abstract: An apparatus for adjusting a lockout time in a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock and generates adjusted and encoded vectors, both indicating a first time period. A select vector is employed to select a delayed version of the reference clock that lags the reference clock by a second time period, which is slightly less than a number of reference clock cycles. The select vector is reduced in value to generate the adjusted vector. The receivers are coupled to the delay-locked loop. Each of the one or more receivers receives the encoded vector and a corresponding strobe, and locks out reception of the corresponding strobe for the first time period following transition of the corresponding strobe. The encoded vector is employed to determine the first time period by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate the lockout time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Abstract: A microprocessor breakpoint checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.

Abstract: Spread spectrum clock generation (SSCG) using phase modulation. A first clock signal having a first frequency spectrum may be modulated using phase modulation to produce a second clock signal. The phase modulation may include providing a phase modulation profile corresponding to the integrated frequency modulation profile, to adjust a scaling factor used in obtaining the second clock signal. The phase modulation profile may be provided in the form of a pulse or pulses, which may be injected through pulse density modulation or pulse width modulation at the output of a phase frequency detector comprised in a phase locked loop circuit used in generating the second clock signal. This modified phase modulation technique removes the down spread limitation present in traditional PM implementations, and also provides better jitter performance and lower cost than traditional PM implementations.

Abstract: The invention discloses Redundant Array of Inexpensive Disks (RAID) systems, utilizing a RAID descriptor having compatibility for different RAID levels. When the RAID system is set to realize RAID 5, the RAID descriptor comprises a first RAID sub-descriptor. When the RAID system is set to realize RAID 6, in addition to the first RAID sub-descriptor, the RAID descriptor further comprises a second RAID sub-descriptor.

Abstract: The present invention is directed to a method, apparatus and system for detecting the mode and the guard interval of a received orthogonal frequency division multiplexing (OFDM) symbol, which includes a guard interval with length Ng, and a useful part with length Nu. Mode is detected by searching for the maximum correlation or statistics value based on one (for example, the shortest one) guard interval length. Further, guard interval is detected by searching for the maximum correlation value based on all guard interval lengths.