Abstract: A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level.

Abstract: This invention discloses a method and system for implementing transparent multi-buffering in multi-GPU graphics subsystems. The purpose of multi-buffering is to reduce GPU idle time. In one example, after rendering a first image by a first GPU in a back buffer, the first image is displayed by flipping to the back buffer. After that, the front buffer and back buffer are exchanged, and then shifting the back buffer and internal buffers in a predetermined sequence. A second image is rendered to current back buffer by a second GPU. The second image is displayed by flipping to a current back buffer. After that, the front buffer and back buffer are exchanged again, and shifting the back buffer and internal buffers again.

Abstract: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.

Abstract: In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

Abstract: A method and system is disclosed for detecting indicators using a multi-stage and multi-threshold detection mechanism so that a mobile terminal can be removed from an idle mode appropriately.

Abstract: A chip for use with both a high-speed bus and a low-speed bus in a computer system includes a test control unit recorded therein a preset address data for determining a transmission path of an external signal in a test mode of the chip; an upstream control unit for transmitting the external signal to the high-speed bus in a normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode; and a downstream control unit for transmitting the external signal to the low-speed bus in the normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode.

Abstract: Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract: A method for correcting gain imbalance error, phase imbalance error and DC offset errors in a transmitter having an OFDM-based I/Q modulator is disclosed. The method employs a compensator prior to the I/Q-modulator to compensate for the gain and phase imbalance and DC offset. The compensator is efficiently updated with the estimated values of gain and phase imbalance and DC offsets obtained by performing the DFT operation in the digital baseband domain while sending a pair of orthogonal test tones to the modulator's inputs from a digital baseband chip, then down converting the RF modulated signal through a nonlinear device and a bandpass filter to a baseband signal, and finally sampling it using an A/D. The delay mismatch, which is mainly generated by lowpass filters between the I and Q branches, is also minimized in this method.

Abstract: Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.

Abstract: Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.

Abstract: A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Abstract: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector.

Abstract: An out-of-order execution in-order retire microprocessor includes a branch information table comprising N entries. Each of the N entries stores information associated with a branch instruction. The microprocessor also includes a reorder buffer comprising M entries. Each of the M entries stores information associated with an unretired instruction within the microprocessor. Each of the M entries includes a field that indicates whether the unretired instruction is a branch instruction and, if so, a tag identifying one of the N entries in the branch information table storing information associated with the branch instruction. N is significantly less than M such that the overall die space and power consumption is reduced over a processor in which each reorder buffer entry stores the branch information.

Abstract: A data prefetcher includes a table of entries to maintain a history of load operations. Each entry stores a tag and a corresponding next stride. The tag comprises a concatenation of first and second strides. The next stride comprises the first stride. The first stride comprises a first cache line address subtracted from a second cache line address. The second stride comprises the second cache line address subtracted from a third cache line address. The first, second and third cache line addresses each comprise a memory address of a cache line implicated by respective first, second and third temporally preceding load operations. Control logic calculates a current stride by subtracting a previous cache line address from a new load cache line address, looks up in the table a concatenation of a previous stride and the current stride, and prefetches a cache line using the hitting table entry next stride.

Abstract: A data transceiver and method thereof are disclosed. The data transceiver generates a gated control signal according to a valid signal and a clock signal. The packets are outputted according to the gated control signal.

Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.

Abstract: Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer.