Abstract: An apparatus has a queue, each entry stores a different line of a stream of instruction bytes and accumulated prefix information associated with each instruction byte.

Abstract: An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decode logic decodes the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator and receives a corresponding taken indicator for each of the instruction bytes. The taken indicator is true if a branch predictor predicted the instruction byte is the opcode byte of a taken branch instruction. The decode logic generates a corresponding bad prediction indicator for each of the instruction bytes. The bad prediction indicator is true if the corresponding taken indicator is true and the corresponding opcode byte indicator is false. The decode logic sets to true the bad prediction indicator for each remaining byte of an instruction whose opcode byte has a true bad prediction indicator.

Abstract: An apparatus detects a load-store collision within a microprocessor between a load operation and an older store operation each of which accesses data in the same cache line. Load and store byte masks specify which bytes contain the data specified by the load and store operation within a word of the cache line in which the load and data begins, respectively. Load and store word masks specify which words contain the data specified by the load and store operations within the cache line, respectively. Combinatorial logic uses the load and store byte masks to detect the load-store collision if the data specified by the load and store operations begin in the same cache line word, and uses the load and store word masks to detect the load-store collision if the data specified by the load and store operations do not begin in the same cache line word.

Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.

Abstract: A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

Abstract: A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit formed by a capacitor-connected MOS of a same type as that of the corresponding driving unit. Each charge unit is controlled by an auxiliary signal inverse to the input signal. When a level transition occurs in the input signal, the charge unit can compensate charge injection and clock feed-through caused by the driving unit at the output node, and form peaks for pre-emphasis. In this way, a better transmission property can be realized by using a simpler and low-power circuit design.

Abstract: A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture.

Abstract: A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control circuit records the flushed buffer(s) in the buffering unit when receiving the flush request and outputs a flush acknowledge signal to indicate to the first master device that the buffering unit has been flushed when all the plurality of buffers have been flushed once after the flush request has been received.

Abstract: The invention provides a Code Division Multiple Access (CDMA) receiver for sampling a received CDMA signal into a plurality of samples. The CDMA receiver comprises a sampling control module, a code generator, and a plurality of despreaders. The sampling control module delays the samples for a plurality of different delay lengths to obtain a plurality of delayed samples respectively corresponding to each of the delay lengths, and adjusts timing of a sampling trigger signal and a code generation trigger signal according to a sampling timing adjustment signal. The code generator generates a despreading code according to the code generation trigger signal. Each of the despreaders is configured for decimating the delayed samples corresponding to each delay lengths according to the sampling trigger signal to obtain a plurality of decimated delayed samples, and despreads the decimated delayed samples with the despreading code to obtain a plurality of output signals.

Abstract: A spread spectrum receiver in a communication system compensating channel response, and the method thereof is disclosed. The spread spectrum receiver comprises a multiplier, a filter, a data channel correlator, a delay, and a channel compensator. The multiplier (322) multiplies despread pilots (320) with conjugate of pilot pattern (324) to provide channel estimates. The filter (323) filters the channel estimates from the multiplier (322). The data channel correlator (30) despreads data symbols in a data channel. The delay module (38), coupled to the data channel correlator (30), delays the despread data symbols for a period. The channel compensator (34), coupled to the filter (323) and the delay module (38), compensates the delayed despread data symbols with the filtered channel estimates.

Abstract: A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module, making the memory send an interrupt request such that a new packet data can be read into the memory. This results in increased data transmission efficiency in the network interface circuit.

Abstract: A file switching method of a Basic Input/Output System (BIOS) file is disclosed. Upon a received read instruction, a timer for a predetermined timing is initiated, and a first data page having a requested data is read from a first BIOS file. An error correction check on the first data page is performed to check if any error in the first data page. If an error is occurred in the error correction check, repeating the step “reading the first data page”. If number of times of the repeating step exceeds a predetermined number, or if the predetermined timing is expired, a second data page having the requested data is read from a second BIOS file according to the read instruction.

Abstract: A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush request and outputs a flush acknowledgement signal to the first master device in response of that a buffer read pointer of the buffering unit is identical to the recorded buffer write pointer.

Abstract: A peak phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a peak phase error value representing peak phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit remains set until reset so that the longest pulse difference signal is registered to provide the peak phase error.

Abstract: A method of data migration for independent storage device expansion and adaptation is disclosed. The method migrates user data of a first storage unit being pre-expanded or pre-adapted to relevant regions of a second storage unit being post-expanded or post-adapted in multiple batches and includes the following steps. A number corresponding to a start data stripe of the first storage unit is provided in each batch. A data stripe migration quantity is determined. Data stripe user data of the determined data stripe migration quantity subsequent to and including the start data stripe of the first storage unit is duplicated and stored in relevant regions of the second storage unit. Subsequent to duplicating and storing each batch, the original user data of data stripes of the determined data stripe migration quantity subsequent to and including the start data stripe of the first storage unit remains undamaged.

Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.

Abstract: A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.

Abstract: A system and method of auto-configuration for the instrument setting of a multimedia apparatus is disclosed. All available output modes are used to show multimedia information to a user by means of automatically switching and setting configurations among connected terminals. The user may select one configuration having the most perfect output quality and then set the multimedia apparatus to be operated under the selected configuration and associated connected terminal. Since connecting or setting the apparatus incorrectly can be effectively avoided, a user will not wonder what is wrong or even think that the multimedia apparatus has malfunctioned.

Abstract: A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and controls clock generation circuitry of the microprocessor to output a lower one of its M core clock signal frequencies as necessitated by a transition to the next lower output voltage level until the temperature drops below the first temperature. The control circuit detects that the temperature has dropped below a second temperature and responsively iteratively controls the voltage source to output a next higher output voltage level and controls the clock generation circuitry to output a higher core clock signal frequency as permitted by the next higher output voltage level until the operating temperature rises above the second temperature. The M frequencies comprise a highest, lowest, and plurality of intermediate frequencies.

Abstract: A voltage regulation module which includes an adjustable voltage which reduces the positive supply voltage and increases the negative supply voltage during a lower power mode. The voltage regulation module includes a voltage generator which provides an N-type substrate bias voltage at the normal operating voltage level of the positive supply voltage and which provides a P-type substrate bias voltage at the normal operating voltage level of the negative supply voltage during the lower power mode. Thus, the supply voltage levels are adjusted rather than the substrate bias voltages during the lower power mode. The voltage generator may be implemented as a voltage regulator, or may be implemented as a bias generator or charge pump or the like.