Abstract: The method for estimating recording power Pow_tilting of a tilting part of a tilting disk is shown based on a power compensation formula: Pow_comp=A*(A*K). After a focus error (FE) signal of the tilting part of the tilting disk is manipulated as a focus servo output (FOO) signal, the parameter A is derived by low-pass filtering the FOO signal. Thereafter, another parameter K is then derived from a reference lookup table by using curve fitting approach based on parameter A such that the power compensation Pow_comp could be estimated by substituting parameters A and K into the above formula. A recording power Pow_tilting of the tilting part of the tilting disk could be estimated by adding a given recording power Piwrtpwr to the power compensation Pow_comp.

Abstract: A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configured to receive from the load unit a physical address of a first cache line that includes the page table entry specified by the load request. The prefetch unit is further configured to responsively generate a request to prefetch into the cache memory a second cache line. The second cache line is the next physically sequential cache line to the first cache line. In an alternate embodiment, the second cache line is the previous physically sequential cache line to the first cache line rather than the next physically sequential cache line to the first cache line.

Abstract: A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.

Abstract: An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a second P+-doped region and a second N+-doped region, both of which are connected to a power supply voltage; and a third P-well installed on the substrate and having a third N+-doped region, a third P+-doped region, and a fourth N+-doped region, all of which are for input/output signals.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: A ball grid array (BGA) package includes a substrate and a chip. A bottom surface of the substrate includes a central area and a marginal area. Several source balls are disposed in the central area. Several ball groups are disposed in the marginal area. Each ball group includes one ground ball and at most three signal balls. The chip is disposed on a top surface of the substrate and electrically connected to the substrate.

Abstract: A video playing device includes a TV encoding circuit, a pre-setting circuit, and a video processing circuit. The TV encoding circuit encodes a first picture and generates a VSYNC signal. The pre-setting circuit is electrically connected with the TV encoding circuit, and receives the VSYNC signal to set a pre-setting signal. The pre-setting signal is enabled before the TV encoding circuit encodes a second picture. The video processing circuit is electrically connected with the pre-setting circuit, and receives the pre-setting signal to execute a video setting process for setting the video playing device to play the second picture. The video setting process is completed before the second picture is encoded. The pre-setting signal is adjustable such that the video setting process is completed before the second picture is played.

Abstract: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.

Abstract: Multi-view video switching control methods and systems are disclosed. It is determined whether a VBI (vertical blanking interval) of signals respectively transmitted by a first GA (graphic array) and a second GA is detected. The video source of first and second GAs belongs to the same first video source. If the VBI corresponding to first GA is detected first, the video source of first GA is switched to a second video source, and the video source of second GA is switched to the second video source if the VBI corresponding to second GA is then present. If the VBI corresponding to second GA is detected first, the video source of second GA is switched to the second video source, and the video source of first GA is switched to the second video source if the VBI corresponding to first GA is then present.

Abstract: Methods for processing multi-source data. It is determined whether any data exists at a position pointed by a first pointer corresponding to a first data source in a queue. If so, an overlapped portion of data read from the first data source and the data pointed by the first pointer in the queue is processed with the data in the queue, and stored to the queue from the position pointed by the first pointer. The first pointer re-points to a position subsequent to the processed data in the queue. A non-overlapped portion of the data read from the first data source and the data pointed by the first pointer in the queue is stored to the queue from the position pointed by the first pointer. If the data in the queue is processed with data from each of the data sources, the processed data is output to a data processing system for further processing.

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract: A mix mode multimedia player having audio scenery and video scenery thereof being controlled individually comprises a playback manager module, and a presentation engine module. The playback manager module for generating audio-format play list, video-format play list, and audio-video interlaced-format play list according to user settings. The user settings includes a plurality of media file's names that user desires to play. The presentation engine module has an audio scene state machine, and a video scene state machine, wherein the presentation engine module provides corresponding play sequences to the audio scene state machine, and the video scene state machine. Furthermore, the audio scene state machine can thus play the media files with audio format and said video scene state machine can thus play said media files with video format.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software.

Abstract: A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: A method and system is disclosed for detecting paging indicators using a multi-stage and multi-threshold detection mechanism so that a mobile terminal can be removed from an idle mode appropriately. After receiving a first paging indicator, it is determined whether a first indicator measurement corresponding to the first paging indicator is between a first and a second predetermined thresholds. After receiving a second paging indicator which may be a temporal diversity counterpart of the first paging indicator, a second indicator measurement derived based on both the first and second paging indicators is compared against a third predetermined threshold, wherein the mobile terminal is removed from the idle mode when both comparisons are appropriately conducted.

Abstract: An apparatus and method for initializing an elastic buffer are provided. The elastic buffer, a FIFO buffer, outputs and writes data according to a reading index and a writing index, respectively. First, a random number is generated. Then, the writing index is determined according to the random number and the reading index. Finally, the elastic buffer is initialized according to the writing index and the reading index.

Abstract: An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.