Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Abstract: A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal.

Abstract: During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.

Abstract: An embodiment of an impedance adjustment apparatus is disclosed. For this embodiment of an impedance adjustment apparatus, a differential driver circuit has an input port, a first output port, a second output port, a first bias node, and a second bias node. A first impedance-voltage device is coupled to provide a first bias voltage to the first bias node. A second impedance-voltage device is coupled to provide a second bias voltage to the second bias node. A first analog voltage source is coupled to provide a first analog voltage to the first impedance-voltage device, and a second analog voltage source is coupled to provide a second analog voltage to the second impedance-voltage device.

Abstract: A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies packet fields. The programmable compute pipeline includes a sequence of stages beginning with an initial stage. The initial stage includes an operand selector that extracts a data vector from each packet. The operand selector is programmable to extract the data vector that includes each field specified in the respective set for the type of each packet. Each stage except the initial stage inputs a first version of the data vector and each stage outputs a second version of the data vector. Each stage except the initial stage generates the second version of the data vector that replaces a part of the first version of the data vector with a result that the stage computes from the part.

Abstract: In an embodiment of an equalizer, a demodulator for MMSE-SIC receives a symbol vector to provide first information. A decoder receives the first information to provide second information to the demodulator. The decoder iteratively processes the first information to provide the second information. The demodulator and decoder are coupled in a loop for feeding back the second information for iteratively refining the first information. A detection-cancellation block of the demodulator receives the symbol vector to provide an equalized vector. A channel pre-processor block of the demodulator receives an initial vector output of the detection-cancellation block for the symbol vector for a demodulating-decoding iterative sequence to provide a weight vector. The channel pre-processor block provides an approximation using a fixed matrix to generate the weight vector. The detection-cancellation block receives the weight vector for equalization of the symbol vector in order to provide the equalized vector.

Abstract: A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial portion of the message fills n complete segments, where n<N. The method further includes processing the initial portion of the message placed on the bus to compute a CRC while compensating for any data on the bus preceding the initial portion, and subsequently processing one or more following portions of the message placed on the bus to update the CRC. A final portion of the message is processed to update the CRC by separately processing complete segments that do not fill the bus and any bytes that do not completely fill the last segment.

Abstract: A systolic array for Cholesky decomposition of an N×N matrix is described. A plurality of processing cells, including a corner cell, N?1 boundary cells, and (N2?3N+2)/2 internal cells, are arranged into N?1 rows and N columns of processing cells. Each row of processing cells is configured to calculate elements of a respective column of a lower triangular output matrix. Each processing cell of each row is configured to determine a value of a respective element of the lower triangular output matrix using a value of an element calculated in a previous processing cell of the row.

Abstract: A nano-electric switch includes a cavity base, a confinement wall, and a cavity top defining a cavity. A floating conductive bridge movable within the cavity completes an electrical circuit between a first electrical contact and a second electrical contact in a first selectable position, and breaks the electrical circuit in a second selectable position.

Abstract: Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.

Abstract: Approaches for generating a hardware definition from a program specified in a high-level language. In one approach, a first set of blocks of instructions in the high-level language program is identified. Each block in the first set is bounded by a respective loop designation in the high-level language. For each block in the first set, an associated respective second set of one or more blocks of the program is identified. Each block in the second set is outside the block in the first set. A hardware definition of the program is generated and stored. For each block in the first set, the hardware definition specifies power-reducing circuitry for one or more blocks in the associated second set. The power-reducing circuitry is controlled based on a status indication from the hardware definition of the block in the first set.

Abstract: In one embodiment of the present invention, a method for determining a phase alignment of a Bayer color filter array is provided. A quincunx lattice of the color filter array corresponding to a first color component is determined from an input frame of image data. Elements of the color filter array corresponding to first and second rectangular lattices of the color filter array are selected. Second and third color components corresponding to elements of the first and second rectangular lattices are determined from the sample values in an input frame of image data.

Abstract: A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency.

Abstract: An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass gate.